The Circuit Designer's Companion - diagramas.diagram...

142 The Circuit Designer’s CompanionV GSI Dt rC GDt donI Dt ft doffV GSthV inR GC GSV GSV inFigure 4.33 Gate switching capacitance and waveformsV GS time constants determined by R G · C GS and R G · C GD(ignoring effect of changing drain voltage)VMOS may have an input capacitance of 200pF. If the switching voltage threshold ofthe VMOS is 3V, then the time taken to reach this level is C·V/I = 150ns. Note thatmany VMOS devices are characterised for R DSon at V GS = 10V, and should not be drivendirectly from 5V logic. Worst-case combinations of supply voltage, output level andVMOS threshold will lead to the VMOS being driven on the knee of its “on”characteristic, with unpredictable and high values of R DSon . Families of “logiccompatible”VMOS are available, characterised at V GS = 5V.However, this is by no means the end of the story; the actual switching waveformsare complicated by feedback of the drain waveform through the drain-gate (Miller)capacitance C GD . This also has to be charged by the gate drive circuit, along with C GS .Charge time for the Miller capacitance is larger than that for the gate to sourcecapacitance C GS due to the rapidly changing drain voltage during turn-on.MOSFET manufacturers now characterise this aspect of their devices using theconcept of gate charge. The advantage of using gate charge is that you can easilycalculate the amount of current required from the drive circuit to switch the device onin a desired length of time, since Q (charge) = time x current. For example, a devicewith a gate charge of 20nC can be turned on in 20µsec if 1ma is supplied to the gate orit can turn on in 20nsec if the gate current is increased to 1A. So keeping R G low and I Ghigh improves switching times significantly. Various techniques can be employed tothis end; Figure 4.34 shows some of them.Gate-source overvoltageBesides switching times, other factors call for a low dynamic impedance from the gatedrive circuit. Excessive V GS will punch through the gate-source oxide layer and causepermanent damage. Transient gate-source overvoltages can be generated by large drainvoltage spikes (caused, for instance, by another device connected to the drain, or byinduced transients) coupled through the drain-gate capacitance. If the dynamic drivecircuit impedance is high − as might be the case if the gate is driven from a pulsetransformer − the transient amplitude will only be limited by the potential divider effectof C GD and C GS . A typical ratio of these values is 1:6, so that a 300V drain transientwould be reflected as a 50V gate transient, which is quite enough to destroy the gate.The simple precaution if such transients are anticipated (especially if the drain isconnected to an external circuit) is to specify a device with an integral zener gate