The Circuit Designer's Companion - diagramas.diagram...

144 The Circuit Designer’s Companiongate drive return connectiondirectly to terminalstray source lead inductancedevelops series voltage withdrain-source di/dtFigure 4.35 Preventing source lead inductance from affecting V GV+clamping diodeL S = stray inductanceI DZ LV DSL S overvoltageL S= −ΣL s dI D /dtC SV+ringing due to straydrain capacitance C SFigure 4.36 Drain-source turn off transient4.5.4 Switching speedHigh switching speeds, while desirable for minimising power losses, have two highlyundesirable side effects. They generate significant electromagnetic interference (EMI)and they also generate drain-source overvoltage spikes. EMI is primarily controlled bylayout, filtering and screening and is the subject of Chapter 8. Here, it is merely notedas a factor opposing the trend to faster switching.Drain-source overvoltages are generated when current flowing through an inductiveload is switched off quickly (cf section 3.4.4). Even when the main load is noninductiveor is clamped, stray inductance can cause significant transients at the currentlevels and switching speeds offered by VMOS devices (Figure 4.36). For instance, 20Abeing switched across 0.5µH in 50ns will create a spike of 200V. Additionally, theforward recovery of the clamping diode may be insufficient to catch the leading edgeof the main inductive transient. As well as ensuring that all connections in the high-di/dt area are as short as possible for minimum inductance, a drain-source clamping zeneror snubber local to the device is a useful precaution.4.5.5 On-state resistanceFinally, it is also wise to remember when running a VMOS device in the on-state at highpower that dissipation is thermally limited. This means that I 2 R must be restricted to