The Circuit Designer's Companion - diagramas.diagram...

172 The Circuit Designer’s CompanionV in0V0V Vinput overdriveinFigure 5.18 Comparator overdriveoffset is varied to give different overdrive values. The greater the overdrive, the morecurrent is available from the differential input stage to propagate the change of statethrough to the output, although beyond a certain point there is no gain to be had fromincreasing it. Small overdrives can lead to suprisingly long response times and youshould check the data sheet carefully to see if the device is being specified in similarfashion to how your circuit will drive it.The specification test assumes that the step function has a much shorter rise timethan the response to be measured. Response time specs are virtually meaningless whenthe comparator is driven by slow rise time analogue signals. We shall discuss this morefully under the heading of hysteresis.Load impedanceThe output load resistance R L (for open-collector types) and capacitance C L have amajor influence on the output slewing rate. The capacitance includes the device outputcapacitance, circuit strays and the input capacitance of the driven circuit (this last isusually the most significant). The slewing rate is determined by the current that isslow rising edgeR LC LCLFigure 5.19 Output slewing vs. load capacitanceavailable to charge and discharge the capacitance, following the rule dV/dt = I/C. Forthe negative-going transition this current is supplied by the output sink transistor and isin the region of 10−50mA, assuring a fast edge, but the current available to charge thepositive transition is supplied by the pull-up device or resistor and may be an order ofmagnitude lower. The choice of output resistor directly affects the positive-going risetime (Figure 5.19) and the power dissipation of the circuit.The advantages of the active lowOn this latter point, it is worth remembering that if you expect low-duty-cycle pulses atthe output, want low power drain and a fast leading edge and have a choice of logicpolarity, that the preferable configuration is to use an active-low output as in Figure5.20(a). The signal is normally off so that power drain is low, and the leading edgetransition depends on the output transistor rather than the pull-up. If a fast trailing edgeis also needed, the pull-up can be reduced in value without significantly affecting power