The Circuit Designer's Companion - diagramas.diagram...

304 The Circuit Designer’s CompanionAs well as performing boundary tests of each IC, ICs may also be instructed via thescan path to perform a built-in self test operation, and the results inspected via the samepath. Boundary scan is not limited to individual ICs; several ICs on a board willnormally be linked together to offer an extended scan path (which could be partitionedor segmented to optimise testing speed). The whole board itself could be regarded asthe system to be tested, with a scan path encompassing the connections at the board’sboundary, and boundary-scan cells implemented at these connections using ICsdesigned for the purpose.DevicesEvery IEEE Std 1149.1-compatible device has four additional pins – two for controland one each for input and output serial test data. These are collectively referred to asthe “Test Access Port” (TAP). To be compatible, a component must have certain basictest features, but the standard allows designers to add test features to meet their ownunique requirements. A JTAG-compliant device can be a microprocessor,microcontroller, PLD, CPLD, FPGA, ASIC or any other discrete device that conformsto the 1149.1 specification. The TAP pins are:• TCK – Test Clock Input. Shift register clock separate from the system clock.• TDI – Test Data In. Data is shifted into the JTAG-compliant device via TDI.• TDO – Test Data Out. Data is shifted out of the device via TDO.• TMS – Test Mode Select. TMS commands select test modes as defined inthe JTAG specification.The 1149.1 specification stipulates that at every digital pin of the IC, a single cellof a shift-register is designed into the IC logic. This single cell, known as the Boundary-Scan Cell (BSC), links the JTAG circuitry to the IC’s internal core logic. All BSCs ofa particular IC constitute the Boundary-Scan Register (BSR), whose length is of coursedetermined by the number of I/O pins that IC has. BSR logic becomes active whenperforming JTAG testing, otherwise it remains passive under normal IC operation. A1-bit bypass register is also included to allow testing of other devices in the scan path.You communicate with the JTAG-compliant device using a hardware controllerthat either inserts into a PC add-in card slot or by using a stand-alone programmer. Thecontroller connects to the test access port on a JTAG-compliant PCB – which may bethe port on a single device, or it may be the port created by linking a number of devices.You (or your test department) then must write the software to perform boundary scanprogramming and testing operations.As well as testing, the boundary scan method can be used for various other purposesthat require external access to a PCB, such as flash memory programming.Deciding whether or not to use boundary scanAlthough the boundary scan method has enormous advantages for designers faced withthe testing of complex, tightly packed circuits, it is not without cost. There is asignificant logic overhead in the ICs as well as a small overhead on the board inimplementing the TAP, and there is the need for your test department to invest in theresources and become familiar with the method as well as programming each product.As a rough guide, you can use the following rule † (relating to ASIC design) to decideon whether or not the extra effort will be cost effective:† From “IEEE Std 1149.1 (JTAG) Testability Primer”, Texas Instruments, 1997