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DISCOVERING<strong>THE</strong> LASTUNREALIZEDPOWER REDUCTIONPOWER-OPTIMIZED ARCHITECTURES HELP <strong>ENGINEER</strong>S DESIGNING CHIPS WITH BLOCKS THAT CANPOWER DOWN OR OPERATE AT REDUCED FREQUENCIES AND VOLTAGES.BY JAY CHIANG • SYNOPSYSPower has become one of the most importantdesign criteria for almost all design projects,and the industry, in response, has invested alot of effort to address this challenge. Consequently,we have seen a plethora of lowpowerdesign techniques and new technologiesemerge. Some of these techniques arerelatively easy to adopt. For example, clockgating and multiple-threshold-voltage cellshave become mainstream design practices because they are effective.In addition, EDA tools can automate their implementation.Some techniques, on the other hand, require more planning.For example, design engineers can group SOC (system-onchip)circuits into multiple blocks so that they can power downsome blocks or operate them at reduced frequencies or voltageswhen operating conditions allow it. Although these more advancedtechniques take more deliberate effort to implement,design engineers are increasingly employing them to meet themore stringent power requirements in next-generation chips.When applying low-power designtechniques, design engineers typicallyconcentrate on only the few modules,such as embedded processors andon-chip memories, that consume morepower than the other blocks. Althoughthis focus is necessary, it is incomplete.Engineers may often overlook thefact that many low-power-consumingblocks frequently have a greater impacton energy consumption than their power-consumptionnumber suggests. If youcorrectly plan a chip’s power-managementstrategy, the power-consumptionprofile and energy-consumption profileshould not correlate closely. You shouldkeep the active period of the high-power-consumingmodules as short as possible.The modules that remain poweredfor a long time should not consume toomuch power. Even though these modulesconsume less power than otherblocks, they consume a higher propor-24 EDN | SEPTEMBER 9, 2010
Agilent InfiniiVision 7000B Series (MSO and DSO models) Bandwidth: 100 MHz - 1 GHz40% bigger screen.Tektronix 4000 Series475,000 times faster…Yes, really.Waveform updaterate wvfm/s100,00080,00060,00040,00020,0000Agilent MSO7104BTektronix MSO4104Waveform Update Rate Comparison95,00050,000Baseline: Analogchannels only,timebase20 ns/div.60,0002,300Changetimebaseto 10 ns/div95,000125Turn onMSOchannels95,00035Enabledeepmemory95,0000.2Turn onserialdecodeNotes: · Measurements taken on same signal using Agilent MSO7104B and Tektronix MSO4104 .· Memory depth = display window X sample rate with up to 8 Mpts on Agilent.· Tektronix measurements taken with version 2.13 firmware.· Screen images are actual screen captures, and scopes are shown to scale.A scope’s real world performance depends on morethan just bandwidth and sample rates. It takes anultra fast update rate to capture infrequent events anddisplay the most accurate signal detail. That’s whereAgilent 7000B Series scopes really stand out. Thanksto a proprietary chipset, you get faster update ratesnot only in analog mode, but in every mode. That’swhy you see greater signal detail. That’s Agilent.© 2010 Agilent Technologies, Inc.Agilent and ourDistributor NetworkRight Instrument.Right Expertise.Delivered Right Now.888-852-7234www.rselectronics.comAre you using the best scope?Take the 5-minute Scope Challenge.Visit www.agilent.com/find/faster
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