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SELECTA(a)BSELECTThe resulting increased area sometimesoffsets the entire power gain from theLSB truncation. For optimal results,you must consider RTL-coding practicesthat allow the merging of datapathblocks to avoid unnecessary binaryconversions (Figure 1b).Some design engineers also try tocode isolation logic in front of the datapathlogic so that they can suppress theswitching and transition of the datapathtree until there is valid data. Dependingon the input-data profile and how frequentlythe data is valid, this approachcould save significant dynamic power.The concept, operand isolation, is similarto clock gating, except that it takesplace on the datapath instead of theclock paths (Figure 2). The concept,also known as data gating or datapathgating, is appealing, but it is sometimesdifficult to implement in practice. Unlikeclock gating, adding isolation logicto datapaths increases the path delay.This timing overhead can make ittricky to close timing. Some RTL-synthesistools can automatically insert theisolation logic; however, engineers donot widely use the feature because it degradestiming.E0 0Figure 1 Multiple carry-propagation adders for every fragmenteddatapath block (a) increase power consumption.Merging datapath blocks and providing one carry-propagationadder for each merged block (b) avoids unnecessarybinary conversions.A(b)B+EAN ALTERNATIVE APPROACHDatapath generators traditionallyproduce the most area-economic architecturesthat still meetthe timing constraints.Engineers then optimizethe generated designsfor power at thegate level. At this level,the scale of optimizationinvolves only a fewgates. The flows don’tprovide power-optimizedarchitectures, sosome designers manuallycode them in lowlevelRTL, which canhinder datapath optimizationand degradethe quality of results.To improve this situation,the first step is tounderstand what kindof datapath architecturesconsume less powerso that you can usethe knowledge to createmore low-power architectures.Second, youshould characterize the power costs ofthe datapath structures at a high levelso that you can fully consider the powerconsequences when making architecturaldecisions.Examples include the power-stingyarchitectures of the Synopsys (www.synopsys.com) DesignWare minPowercomponents. These low-power datapatharchitectures are flatter, shallower,and more balanced than traditionalarchitectures to produce fewer spurioustransitions. When these unwantedtransitions occur, datapath structureswith smarter cell selections can limittheir propagation. For example, insteadof using common XOR-based datapathcells, such as full adders or XOR-basedbooth encoders, the manpower componentsemploy architectures that favormore AND or NAND cells so thatfewer transitions ripple throughout thedatapath tree.Integrating these power-friendly architecturesyields some advantages.Aside from being easier to use, thesearchitectures allow designers to capturepower-saving opportunities thatare hard to realize with a manual approach.Because power consumptiondepends on operating conditions, it isnot enough to consider the circuit architectureoutside the design’s contextor independently of circuit switching.Vinculum VNC2SPEED.FLEXIBILITY.PERFORMANCE.A programmable system-on-chipUSB 2.0 Host / Slave controller.- Dual channel USB 2.0 interface, handlesall USB host and data transfer functionsin single IC.- On-chip 16-bit Harvard architectureMCU core with 256 Kbyte Flash and16kbyte RAM.- External UART, FIFO, SPI Slave, SPI Master,GPIO and PWM interfaces.- Vinculum-II software development toolsavailable for user application development.- Multiple package size options including VNC1Lbackwards compatible package option.- Targeted for range of USB applications, fromportable media devices and cell phones toindustrial and automotive applications.Vinculum-II evaluation modules- V2DIP1/2 - Miniature VNC2 DevelopmentModule with Single or Dual USB Connectors- V2-EVAL - Complete Evaluation &Development Kit for VNC2- VNC2 Debug ModuleUSB MADE EASYwww.ftdichip.com