VOICE OF THE ENGINEER - ElectronicsAndBooks

tion of energy once you factor in theirextended active time.Consider a hypothetical cellularphonedesign. Under typical usage, thecellular phone is mostly in standby mode.During standby, most circuits, except thewireless receiver or receivers, are off. Althoughstandby mode consumes onlya fraction of the power that the othermodes consume, it still consumes 36%of the total energy, after factoring in theactive period. In other words, it pays dividendsto aggressively reduce power forcircuits that are active in the standbymode because it can lead to significantsavings in battery life (Table 1).Such opportunities for energy reductionexist in most SOCs. In general, ifthe chip has multiple power domains, ithas multiple power modes. If you identifythe power modes that are most active,you can isolate the circuits thathave higher impact on the chip’s energyconsumption, and you can moreaggressively pursue power reduction inthese focused areas to reduce the overallenergy footprint of the chip.Analysis of these circuits in furtherdetail uncovers some interesting characteristics.These modules must remainon for extended periods because theyperform essential functions for the chipin that operating mode. They are oftencontinuously calculating data or processingsignals. In addition to the cellular-phoneexample, other circuits, suchas audio or video processors in playbackor talk mode and signal-processingblocks, such as equalizer, modulation,or cryptology units, in wireless and networkingapplications, have more datapathcontent than control logic andcan benefit considerably from low-powertechniques.If you consider the technology horizon,a new generation of connected devicesaiming to deliver better user experiencesand higher data rates is drivingmany new design starts. Consequently,these new projects will demand higherAT A GLANCE↘ Design engineers are increasinglyemploying advanced techniquesto meet the more stringent powerrequirements of next-generationchips.↘ It pays dividends to aggressivelyreduce power for circuits that areactive in standby mode because itcan lead to significant savings inbattery life.↘ Power gating isn’t feasible forcircuits that must continuouslyremain active, so the only choice isto make the circuit intrinsically lowpower.↘ Traditionally, datapath generatorsproduce the most area-economicarchitectures that still meet the timingconstraints.↘ Because power is a physicaldomaincharacteristic, your standardcelllibrary can affect the power-optimizationresult.audio quality, higher video resolution,more pixel support, more complex signalprocessing, faster data rates, and soforth. Increases in the size and complexityof the signal-processing blocksin turn lead to a higher energy footprintin the new designs. The impact of thisdesign complexity requires design engineersto more closely manage the powerconsumption for these blocks.LOW-POWER DATAPATHSPower gating isn’t feasible for circuitsthat must continuously remain active,so the only choice is to make the circuitintrinsically low power. The firststep is to lower the voltage, the operatingfrequency, or both without missingthe performance target. However,slower clock frequencies mean deeperlogic levels, and these circuits usuallyinclude more datapath logic than controllogic. Datapath logic is notoriouslyTABLE 1 SAMPLE POWER MODES AND ENERGY CONSUMPTIONPower modePower consumption(mW)Time budgetedin mode (%)Energy-consumptionprofileStandby 40 90 36Audio 400 3 12Phone 500 5 25Video 1200 2 24prone to glitches—unwanted transitionsthat settle before the next clockedge—and switching because any spurioustransitions propagate downstreamand ripple throughout the entire datapathtree. Although glitches pose nofunctional issues, these transitions stillconsume power.It is critical to avoid increasing powerin other areas while reducing it in onearea. Making this power-reduction approachmore effective requires more balanced,shallower architectures that canlimit the propagation of the transitions.Although most EDA tools do an adequatejob producing timing- and areaoptimizedarchitectures that designerslater optimize for power at the gate level,they are less effective in consideringthe power consequence of architecturalselections upfront.Some design engineers try variousmeans of writing power-optimized architecturesinto RTL (register-transfer-level)code to save power. However, mostlow-power architectural-RTL coding focuseson reducing area, based on the assumptionthat using fewer cells equatesto less power consumption. For example,some design engineers in networkingand multimedia applications truncatethe LSBs (least-significant bits) of thedata when precision is not critical.Although this technique is useful,you must understand the details of howto implement it. Datapaths differ fromother logic circuits in that they performcomputer arithmetic that generatescarries and sums, requiring carry-propagatingadders to add together the carryand sum to produce a binary number.For RTL coded at a high level, EDAtools usually can generate datapath architectures,keeping all the numbers inredundant format—annotating the valueof the number with both carry andsum—until the last level of the output.If you code the datapath at a lowerlevel, you might turn to coding practicesthat divide a larger datapath block intoseveral small ones,forcing the RTLsynthesistools toinsert carry-propagationadders intothe final stageof every smallerblock (Figure 1a),hence increasingarea and delay.26 EDN | SEPTEMBER 9, 2010