TASKING VX-toolset for ARM User Guide

Using the LinkerAddress spacesA logical address space is a memory range for which the core has a separate way to encode an addressinto instructions. Most microcontrollers and DSPs support multiple address spaces. For example, separatespaces for code and data. Normally, the size of an address space is 2 N , with N the number of bits usedto encode the addresses.The relation of an address space with another address space can be one of the following:• one space is a subset of the other. These are often used for "small" absolute or relative addressing.• the addresses in the two address spaces represent different locations so they do not overlap. Thismeans the core must have separate sets of address lines for the address spaces. For example, inHarvard architectures we can identify at least a code and a data memory space.Address spaces (even nested) can have different minimal addressable units (MAU), alignment restrictions,and page sizes. All address spaces have a number that identifies the logical space (id). The followingtable lists the different address spaces for the architecture ARM as defined in arm_arch.lsl.SpaceIdMAUDescriptionlinear18Linear address space.The ARM architecture in LSL notationThe best way to write the architecture definition, is to start with a drawing. The following figure shows apart of the ARM architecture:The figure shows one address space called linear. The address space has attributes like a numberthat identifies the logical space (id), a MAU and an alignment. In LSL notation the definition of this addressspace looks as follows:space linear{id = 1;mau = 8;}map (size=4G, dest=bus:local_bus);The keyword map corresponds with the arrows in the drawing. You can map:• address space => address space (not shown in the drawing)213