ISSCC2015AdvanceProgram

SESSION 4Monday February 23 rd , 1:30 PMProcessorsSession Chair: Atsuki Inoue, Fujitsu, Kawasaki, JapanAssociate Chair: Luke (Jinuk) Shin, Oracle, Redwood Shores, CA4.1 22nm Next-Generation IBM System z Microprocessor 1:30 PMJ. Warnock 1 , B. Curran 2 , J. Badar 3 , G. Fredeman 2 , D. Plass 2 , Y. Chan 2 ,S. Carey 2 , G. Salem 4 , F. Schroeder 5 , F. Malgioglio 2 , G. Mayer 5 , C. Berry 2 ,M. Wood 2 , Y-H. Chan 2 , M. Mayo 2 , J. Isakson 3 , C. Nagarajan 6 , T. Werner 5 ,L. Sigal 7 , R. Nigaglioni 3 , M. Cichanowski 3 , J. Zitz 8 , M. Ziegler 7 , T. Bronson 3 ,G. Strevig 3 , D. Dreps 3 , R. Puri 7 , D. Malone 2 , D. Wendel 5 , P-K. Mak 2 , M. Blake 21IBM Systems and Technology, Yorktown Heights, NY2IBM Systems and Technology, Poughkeepsie, NY3IBM Systems and Technology, Austin, TX4IBM Systems and Technology, Williston, VT5IBM Systems and Technology, Boeblingen, Germany6IBM Systems and Technology, Bangalore, India7IBM Research, Yorktown Heights, NY8IBM Systems and Technology, Hopewell Junction, NY4.2 A 20nm 32-Core 64MB L3 Cache SPARC M7 Processor 2:00 PMP. Li, J. L. Shin, G. Konstadinidis, F. Schumacher, V. Krishnaswamy,H. Cho, S. Dash, R. Masleid, C. Zheng, Y. D. Lin, P. Loewenstein,H. Park, V. Srinivasan, D. Huang, C. Hwang, W. Hsu, C. McAllisterOracle, Redwood Shores, CA4.3 Fine-Grained Adaptive Power Management of the 2:30 PMSPARC M7 ProcessorV. Krishnaswamy, J. Brooks, G. Konstadinidis, C. McAllister,H. Pham, S. Turullols, J. L. Shin, Y. YangGong, H. ZhangOracle, Redwood Shores, CA4.4 Energy-Efficient Microserver Based on a 12-Core 1.8GHz 2:45 PMDS 188K-CoreMark 28nm Bulk CMOS 64b SoC for Big-DataApplications with 159GB/s/L Memory Bandwidth System DensityR. Luijten 1 , D. Pham 2 , R. Clauberg 1 , M. Cossale 1 , H. N. Nguyen 2 , M. Pandya 21IBM Research, Rüschlikon, Switzerland2Freescale Semiconductor, Austin, TXBreak3:00 PM4.5 The Xeon® Processor E5-2600 v3: A 22nm 18-Core Product Family 3:15 PMB. Bowhill 1 , B. Stackhouse 2 , N. Nassif 1 , Z. Yang 1 , A. Raghavan 1 ,C. Morganti 2 , C. Houghton 1 , D. Krueger 2 , O. Franza 1 , J. Desai 2 ,J. Crop 2 , D. Bradley 2 , C. Bostak 2 , S. Bhimji 1 , M. Becker 11Intel, Hudson, MA; 2 Intel, Fort Collins, CO4.6 A 1.93TOPS/W Scalable Deep Learning/Inference Processor 3:45 PMwith Tetra-Parallel MIMD Architecture for Big-Data ApplicationsS. Park, K. Bong, D. Shin, J. Lee, S. Choi, H-J. Yoo, KAIST, Daejeon, Korea4.7 A 409GOPS/W Adaptive and Resilient Domino Register File in 4:15 PM22nm Tri-Gate CMOS Featuring In-Situ Timing Margin and ErrorDetection for Tolerance to Within-Die Variation, Voltage Droop,Temperature and AgingJ. P. Kulkarni, C. Tokunaga, P. Aseron, T. Nguyen Jr, C. Augustine,J. Tschanz, V. DeIntel, Hillsboro, OR4.8 A 28nm x86 APU Optimized for Power and Area Efficiency 4:45 PMDS K. Wilcox 1 , D. Akeson 1 , H. R. Fair III 1 , J. Farrell 1 , D. Johnson 2 ,G. Krishnan 1 , H. McIntyre 3 , E. McLellan 1 , S. Naffziger 2 , R. Schreiber 4 ,S. Sundaram 4 , J. White 11AMD, Boxborough, MA; 2 AMD, Fort Collins, CO3AMD, Sunnyvale, CA; 4 AMD, Austin, TXConclusion5:15 PM16