ISSCC2015AdvanceProgram

TUTORIALSSunday February 22 ndT6: Clock and Data Recovery Architectures and CircuitsThis tutorial provides ground theory and practical strategies for the design of clock-anddata-recoverycircuits. We begin by relating performance metrics such as jitter transfer, jittertolerance, and jitter peaking to CDR loop components and use these relationships to elucidateapplication-specific design challenges and tradeoffs. Following this, we will discuss botharchitectural- and circuit-level techniques to manage/overcome these tradeoffs. Specifically,we would compare different architectures: bang-bang vs. linear, digital vs. analog vs. hybridloops, oscillator vs. phase interpolator, and reference-less vs. reference-based CDRs. We thenpresent frequency-locking techniques and conclude with a case study of a recently reportedCDR.Instructor: Pavan Kumar HanumoluPavan Kumar Hanumolu is an Associate Professor in the Department of Electrical andComputer Engineering at the University of Illinois, Urbana-Champaign. He received the Ph.D.degree from the School of Electrical Engineering and Computer Science at Oregon StateUniversity, Corvallis, in 2006, where he subsequently served as a faculty member until 2013.Dr. Hanumolu’s research interests are in energy-efficient integrated circuit implementation ofanalog and digital signal processing, wireline communication systems, and power conversion.He currently serves as an Associate Editor of the Journal of Solid-State Circuits, and is atechnical program committee member of the VLSI Circuits Symposium, and InternationalSolid-State Circuits ConferenceT7: Basics of Many-Core ProcessorsThis tutorial focuses on the design of many-core processors spanning clients to servers tohigh-performance computing systems in scaled CMOS process. Key circuits and designtechniques are highlighted for robust and variation-tolerant logic, embedded memory arraysand on-die interconnect fabrics. Also presented are design principles that enable a widedynamic voltage-frequency operating range, spanning multi-threaded high-throughputnear-threshold voltage to single-threaded burst performance modes. Fine-grain multi-voltagedesign and power management techniques are covered, along with smart variation-awareworkload mapping schemes to achieve maximum performance under stringent thermal andenergy constraints. Real chip design examples are used to illustrate basic design principlesand practical considerations.Instructor: Vivek DeVivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He isresponsible for providing strategic technical directions for long-term research in future circuittechnologies and leading energy efficiency research across the hardware stack. He has 223publications in refereed international conferences and journals and 195 patents, with 30 morepatents filed (pending). He received an Intel Achievement Award for contributions to integratedvoltage regulator technology. He received a Best Paper Award at the 1996 IEEE InternationalASIC Conference, and nominations for Best Paper Awards at the 2007 IEEE/ACM DesignAutomation Conference (DAC) and the 2008 IEEE/ACM International Conference onComputer-Aided Design (ICCAD). One of his publications was recognized in the 2013IEEE/ACM Design Automation Conference (DAC) as one of the “Top 10 Cited Papers in 50Years of DAC”. He received a Ph.D. in Electrical Engineering from Rensselaer PolytechnicInstitute, Troy, New York. He is a Fellow of the IEEE.T8: Analog Techniques for Nano-power CircuitsThis tutorial presents the design methodology and examples of analog circuits havingnanoampere consumption with application in systems with short activity periods followedlong standby. They are essential for the area of energy harvesting where the amount ofavailable energy can unpredictably change by orders of magnitude. Low load efficiency ofpower management becomes a very important parameter in a wide breadth of applications.Circuit examples include biasing, precision voltage references, oscillators, charge pumps,adaptive speed amplifiers and comparators, LDOs, DCDC converters.6