ISSCC2015AdvanceProgram

SESSION 8Tuesday February 24 th , 8:30 AMLow-Power Digital TechniquesSession Chair: Victor Zyuban, IBM T.J. Watson, Yorktown Heights, NYAssociate Chair: Peter Nilsson, Lund University, Lund, Sweden8.1 An 80nW Retention 11.7pJ/Cycle Active Subthreshold ARM 8:30 AMCortex-M0+ Subsystem in 65nm CMOS for WSN ApplicationsJ. Myers, A. Savanth, D. Howard, R. Gaddh, P. Prabhat, D. FlynnARM, Cambridge, United Kingdom8.2 Batteryless Sub-nW Cortex-M0+ Processor with Dynamic 9:00 AMLeakage-Suppression LogicW. Lim, I. Lee, D. Sylvester, D. BlaauwUniversity of Michigan, Ann Arbor, MI8.3 A 10.5μA/MHz at 16MHz Single-Cycle Non-Volatile 9:30 AMMemory-Access Microcontroller with Full StateRetention at 108nA in a 90nm ProcessV. K. Singhal, V. Menezes, S. Chakravarthy, M. MehendaleKilby Labs, Texas Instruments, Bangalore, IndiaBreak10:00 AM8.4 A 0.33V/-40°C Process/Temperature Closed-Loop Compensation 10:15 AMSoC Embedding All-Digital Clock Multiplier and DC-DC ConverterExploiting FDSOI 28nm Back-Gate BiasingS. Clerc 1 , M. Saligane 1,2,3 , F. Abouzeid 1 , M. Cochet 1,2 , J-M. Daveau 1 ,C. Bottoni 1 , D. Bol 4 , J. De-Vos 4 , D. Zamora 5 , B. Coeffic 1 , D. Soussan 1 ,D. Croain 1 , M. Naceur 6 , P. Schamberger 6 , P. Roche 1 , D. Sylvester 31STMicroelectronics, Crolles, France2Aix-Marseille University, Marseille, France3University of Michigan, Ann Arbor, MI4Universite Catholique de Louvain, Louvain La Neuve, Belgium5MAYA Technologies, Grenoble, France6EASii-IC, Grenoble, France8.5 A 16nm Auto-Calibrating Dynamically Adaptive Clock Distribution 10:45 AMfor Maximizing Supply-Voltage-Droop Tolerance Across a WideOperating RangeK. Bowman, S. Raina, T. Bridges, D. Yingling, H. Nguyen, B. Appel,Y. Kolla, J. Jeong, F. Atallah, D. HansquineQualcomm, Raleigh, NC8.6 Enabling Wide Autonomous DVFS in a 22nm Graphics Execution 11:15 AMCore Using a Digitally Controlled Hybrid LDO/Switched-CapacitorVR with Fast Droop MitigationS. T. Kim, Y-C. Shih, K. Mazumdar, R. Jain, J. F. Ryan, C. Tokunaga,C. Augustine, J. P. Kulkarni, K. Ravichandran, J. W. Tschanz,M. M. Khellah, V. DeIntel, Hillsboro, OR8.7 Dual-Use Low-Drop-Out Regulator / Power Gate with Linear 11:45 AMand On-Off Conduction Modes for Microprocessor On-DieSupply Voltages in 14nmK. Luria, J. Shor, M. Zelikson, A. LyakhovIntel, Yakum, IsraelConclusion12:15 PM22