ISSCC2015AdvanceProgram

FORUM 1Organizer:Co-organizer:Committee:Sunday February 22 nd , 8:00 AMF1: High-Speed Interleaved ADCsStéphane Le Tual, STmicroelectronics, Crolles, FranceBorivoje Nikolic, University of California, Berkeley, CATetsuya Iizuka, University of Tokyo, Tokyo, JapanIchiro Fujimori, Broadcom, Irvine, CATime-interleaved ADCs have become critical components in high-speed wireline and wirelesscommunication systems. This forum will deliver a comprehensive treatment of state-of-theart design techniques for high-speed interleaved ADCs. Topics include transistor-level designtechniques, calibration (estimation & correction), as well as the link between systemspecifications and required ADC performance.TimeTopic8:00 AM BreakfastAgenda8:20 AM Introduction by Chair8:30 AM Interleaved ADCs Through the AgesKen Poulton, Keysight Laboratories, Santa Clara, CA9:20 AM Mismatch Error Correction for High-Resolution,GS/s time-Interleaved ADCsPer Löwenborg, Signal Processing Devices, Linköping, Sweden10:10 AM Break10:35 AM Highly Accurate Adaptive Digital Calibration for High-SpeedHigh-Resolution Time-Interleaved ADCsTakashi Oshima, Hitachi, Tokyo, Japan11:25 AM ADC Interleaving Errors Corrected by Adaptive Post-ProcessingAsad Abidi, University of California, Los Angeles, CA12:15 PM Lunch1:20 PM Specifications vs. Applications: Driving Architectural ChoicesAaron Buchwald, Entropic, Irvine, CA2:10 PM GS/s Time-Interleaved ADCs for Broadband Multi-CarrierSignal ReceptionKostas Doris, NXP, Eindhoven, The Netherlands3:00 PM Break3:20 PM Embedded CMOS ADCs for Optical CommunicationsYuriy M. Greshishchev, Ciena, Ottawa, Canada4:10 PM PanelModerators: Bora Nikolic (UC Berkeley)Dave Robertson (ADI)5:00 PM Closing remarks by Chair8