ISSCC2015AdvanceProgram

SESSION 10Tuesday February 24 th , 8:30 AMAdvanced Wireline Techniques and PLLsSession Chair: Gerrit den Besten, NXP Semiconductors, Eindhoven,The NetherlandsAssociate Chair: Nicola Da Dalt, Infineon, Villach, Austria10.1 A 6Gb/s 6pJ/b 5mm-Distance Non-Contact Interface for 8:30 AMDS Modular Smartphones Using Two-Fold Transmission-LineCoupler and EMC-Qualified Pulse TransceiverA. Kosuge, S. Ishizuka, J. Kadomoto, T. KurodaKeio University, Yokohama, Japan10.2 An FSK Plastic Waveguide Communication Link in 40nm CMOS 9:00 AMW. Volkaerts, N. Van Thienen, P. ReynaertKU Leuven, Leuven, Belgium10.3 A 7.5mW 7.5Gb/s Mixed NRZ/Multi-Tone Serial-Data Transceiver 9:30 AMfor Multi-Drop Memory Interfaces in 40nm CMOSK. Gharibdoust 1 , A. Tajalli 1,2 , Y. Leblebici 11EPFL, Lausanne, Switzerland2Kandou Bus, Lausanne, SwitzerlandBreak10:00 AM10.4 A 5.8Gb/s Adaptive Integrating Duobinary-Based DFE Receiver 10:15 AMfor Multi-Drop Memory InterfaceH-W. Lim 1,2 , S-W. Choi 1,2 , S-K. Lee 2 , C-H. Baek 2 , J-Y. Lee 2 ,G-C. Hwang 2 , Y-H. Jun 2 , B-S. Kong 11Sungkyunkwan University, Suwon, Korea2Samsung Electronics, Hwaseong, Korea10.5 A 5.9pJ/b 10Gb/s Serial Link with Unequalized MM-CDR 10:45 AMin 14nm Tri-Gate CMOSR. Dokania 1 , A. Kern 1 , M. He 2 , A. Faust 1 , R. Tseng 1 , S. Weaver 1 ,K. Yu 1 , C. Bil 3 , T. Liang 3 , F. O’Mahony 11Intel, Hillsboro, OR2Intel, Santa Clara, CA3Intel, Hudson, MA10.6 Continuous-Time Linear Equalization with Programmable 11:15 AMActive-Peaking Transistor Arrays in a 14nm FinFET 2mW/Gb/s16Gb/s 2-Tap Speculative DFE ReceiverP. A. Francese, T. Toifl, M. Braendli, C. Menolfi, M. Kossel, T. Morf,L. Kull, T. M. Andersen, H. Yueksel, A. Cevrero, D. LuuIBM Zurich, Rüschlikon, Switzerland10.7 A 6.75-to-8.25GHz 2.25mW 190fs rms Integrated-Jitter 11:30 AMPVT-Insensitive Injection-Locked Clock Multiplier UsingAll-Digital Continuous Frequency-Tracking Loop in 65nmCMOSA. Elkholy, M. Talegaonkar, T. Anand, P. K. HanumoluUniversity of Illinois, Urbana, IL10.8 A Wideband Fractional-N Ring PLL Using a Near-Ground 11:45 AMPre-Distorted Switched-Capacitor Loop FilterC-F. Liang, P-Y. WangMediaTek, Hsinchu, Taiwan10.9 A 13.1-to-28GHz Fractional-N PLL in 32nm SOI CMOS 12:00 PMwith a DS Noise-Cancellation SchemeM. Ferriss, B. Sadhu, A. Rylyakov, H. Ainspan, D. FriedmanIBM Research, Yorktown Heights, NYConclusion12:15 PM24