VS1063 Hardware Guide - VLSI Solution

VS1063a HW Guide7 HARDWARE REGISTERSThe PLL controller’s operation is optimized for frequencies around 12. . . 13 MHz. If you use an24. . . 26 MHz input clock, set the extra clock divider bit SM_CLK_RANGE in register SCI_MODEto 1 before activating the PLL.It’s recommended to change the PLL rate in small steps and wait for the PLL to stabilize aftereach change. For diagnostic purposes, the PLL clock output (VCO) can be routed to an I/O pinso it can be scanned with an oscilloscope.FCH_PLL_RATE (bits 7:4) control PLL multiplication rate. PLL multiplier is (FCH_PLL_RATE+ 1). When FCH_PLL_RATE is 0, the VCO is powered down and output clock is forced to beinput clock (same as if FCH_PLL_FORCE_PLL = 0).Version: 1.02, 2012-12-05 16