P89C51RB2/P89C51RC2/P89C51RD2 80C51 8-bit Flash ...

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Philips Semiconductors80C51 8-bit Flash microcontroller family16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAMPreliminary specificationP89C51RB2/P89C51RC2/P89C51RD2D0 D1 D2 D3 D4 D5 D6 D7 D8STARTBITDATA BYTEONLY INMODE 2, 3STOPBITSET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)SM0 TO UART MODE CONTROLSM0 / FE SM1 SM2 REN TB8 RB8 TI RISCON(98H)SMOD1 SMOD0 – POF LVF GF0 GF1 IDLPCON(87H)0 : SCON.7 = SM01 : SCON.7 = FESU00044Figure 8. UART Framing Error DetectionD0 D1 D2 D3 D4 D5 D6 D7 D8SM0 SM1 SM2 REN TB8 RB8 TI RISCON(98H)11101 1 XRECEIVED ADDRESS D0 TO D7PROGRAMMED ADDRESSCOMPARATORIN UART MODE 2 OR MODE 3 AND SM2 = 1:INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.Figure 9. UART Multiprocessor Communication, Automatic Address RecognitionSU000451999 Nov 22 18
Philips Semiconductors80C51 8-bit Flash microcontroller family16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAMPreliminary specificationP89C51RB2/P89C51RC2/P89C51RD2Interrupt Priority StructureThe P89C51RB2/RC2/RD2 has a 7 source four-level interruptstructure (see Table 7).There are 3 SFRs associated with the four-level interrupt. They arethe IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (InterruptPriority High) register makes the four-level interrupt structurepossible. The IPH is located at SFR address B7H. The structure ofthe IPH register and a description of its bits is shown in Figure 12.The function of the IPH SFR, when combined with the IP SFR,determines the priority of each interrupt. The priority of eachinterrupt is determined as shown in the following table:The priority scheme for servicing the interrupts is the same as thatfor the 80C51, except there are four interrupt levels rather than twoas on the 80C51. An interrupt will be serviced as long as an interruptof equal or higher priority is not already being serviced. If aninterrupt of equal or higher level priority is being serviced, the newinterrupt will wait until it is finished before being serviced. If a lowerpriority level interrupt is being serviced, it will be stopped and thenew interrupt serviced. When the new interrupt is finished, the lowerpriority level interrupt that was stopped will be completed.PRIORITY BITSIPH.x IP.xINTERRUPT PRIORITY LEVEL0 0 Level 0 (lowest priority)0 1 Level 11 0 Level 21 1 Level 3 (highest priority)Table 7. Interrupt TableSOURCE POLLING PRIORITY REQUEST BITS HARDWARE CLEAR? VECTOR ADDRESSX0 1 IE0 N (L) 1 Y (T) 2 03HT0 2 TP0 Y 0BHX1 3 IE1 N (L) Y (T) 13HT1 4 TF1 Y 1BHPCA 5 CF, CCFnn = 0–4N33HSP 6 RI, TI N 23HT2 7 TF2, EXF2 N 2BHNOTES:1. L = Level activated2. T = Transition activated76543210IE (0A8H)EAECET2ESET1EX1ET0EX0Enable Bit = 1 enables the interrupt.Enable Bit = 0 disables it.BIT SYMBOL FUNCTIONIE.7 EA Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individuallyenabled or disabled by setting or clearing its enable bit.IE.6 EC PCA interrupt enable bitIE.5 ET2 Timer 2 interrupt enable bit.IE.4 ES Serial Port interrupt enable bit.IE.3 ET1 Timer 1 interrupt enable bit.IE.2 EX1 External interrupt 1 enable bit.IE.1 ET0 Timer 0 interrupt enable bit.IE.0 EX0 External interrupt 0 enable bit.SU01290Figure 10. IE Registers1999 Nov 22 19
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P89C51RB2/P89C51RC2/P89C51RD2 80C51 8-bit Flash ...

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