P89C51RB2/P89C51RC2/P89C51RD2 80C51 8-bit Flash ...

Philips Semiconductors80C51 8-bit Flash microcontroller family16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAMPreliminary specificationP89C51RB2/P89C51RC2/P89C51RD2DESCRIPTIONThe P89C51RB2/RC2/RD2 device contains a non-volatile16kB/32kB/64kB Flash program memory that is both parallelprogrammable and serial In-System and In-ApplicationProgrammable. In-System Programming (ISP) allows the user todownload new code while the microcontroller sits in the application.In-Application Programming (IAP) means that the microcontrollerfetches new program code and reprograms itself while in thesystem. This allows for remote programming over a modem link.A default serial loader (boot loader) program in ROM allows serialIn-System programming of the Flash memory via the UART withoutthe need for a loader in the Flash code. For In-ApplicationProgramming, the user program erases and reprograms the Flashmemory by use of standard routines contained in ROM.This device executes one machine cycle in 6 clock cycles, henceproviding twice the speed of a conventional 80C51. An OTPconfiguration bit lets the user select conventional 12 clock timingif desired.This device is a Single-Chip 8-Bit Microcontroller manufactured inadvanced CMOS process and is a derivative of the 80C51microcontroller family. The instruction set is 100% compatible withthe 80C51 instruction set.The device also has four 8-bit I/O ports, three 16-bit timer/eventcounters, a multi-source, four-priority-level, nested interrupt structure,an enhanced UART and on-chip oscillator and timing circuits.The added features of the P89C51RB2/RC2/RD2 makes it apowerful microcontroller for applications that require pulse widthmodulation, high-speed I/O and up/down counting capabilities suchas motor control.FEATURES• 80C51 Central Processing Unit• On-chip Flash Program Memory with In-System Programming(ISP) and In-Application Programming (IAP) capability• Boot ROM contains low level Flash programming routines fordownloading via the UART• Can be programmed by the end-user application (IAP)• 6 clocks per machine cycle operation (standard)• 12 clocks per machine cycle operation (optional)• Speed up to 20 MHz with 6 clock cycles per machine cycle(40 MHz equivalent performance); up to 33 MHz with 12 clocksper machine cycle• Fully static operation• RAM expandable externally to 64 kB• 4 level priority interrupt• 7 interrupt sources• Four 8-bit I/O ports• Full-duplex enhanced UART– Framing error detection– Automatic address recognition• Power control modes– Clock can be stopped and resumed– Idle mode– Power down mode• Programmable clock out• Second DPTR register• Asynchronous port reset• Low EMI (inhibit ALE)• Programmable Counter Array (PCA)– PWM– Capture/compare1999 Nov 222