P89C51RB2/P89C51RC2/P89C51RD2 80C51 8-bit Flash ...

Philips Semiconductors80C51 8-bit Flash microcontroller family16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAMPreliminary specificationP89C51RB2/P89C51RC2/P89C51RD2AC ELECTRICAL CHARACTERISTICS (12 CLOCK MODE)T amb = 0°C to +70°C or –40°C to +85°C, V CC = 5 V ±10%, V SS = 0 V 1, 2, 3 VARIABLE CLOCK 4 33 MHz CLOCK 4SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT1/t CLCL 29 Oscillator frequency 0 33 0 33 MHzt LHLL 29 ALE pulse width 2t CLCL –40 21 nst AVLL 29 Address valid to ALE low t CLCL –25 5 nst LLAX 29 Address hold after ALE low t CLCL –25 5 nst LLIV 29 ALE low to valid instruction in 4t CLCL –65 55 nst LLPL 29 ALE low to PSEN low t CLCL –25 5 nst PLPH 29 PSEN pulse width 3t CLCL –45 45 nst PLIV 29 PSEN low to valid instruction in 3t CLCL –60 30 nst PXIX 29 Input instruction hold after PSEN 0 0 nst PXIZ 29 Input instruction float after PSEN t CLCL –25 5 nst AVIV 29 Address to valid instruction in 5t CLCL –80 70 nst PLAZ 29 PSEN low to address float 10 10 nsData Memoryt RLRH 30, 31 RD pulse width 6t CLCL –100 82 nst WLWH 30, 31 WR pulse width 6t CLCL –100 82 nst RLDV 30, 31 RD low to valid data in 5t CLCL –90 60 nst RHDX 30, 31 Data hold after RD 0 0 nst RHDZ 30, 31 Data float after RD 2t CLCL –28 32 nst LLDV 30, 31 ALE low to valid data in 8t CLCL –150 90 nst AVDV 30, 31 Address to valid data in 9t CLCL –165 105 nst LLWL 30, 31 ALE low to RD or WR low 3t CLCL –50 3t CLCL +50 40 140 nst AVWL 30, 31 Address valid to WR low or RD low 4t CLCL –75 45 nst QVWX 30, 31 Data valid to WR transition t CLCL –30 0 nst WHQX 30, 31 Data hold after WR t CLCL –25 5 nst QVWH 31 Data valid to WR high 7t CLCL –130 80 nst RLAZ 30, 31 RD low to address float 0 0 nst WHLH 30, 31 RD or WR high to ALE high t CLCL –25 t CLCL +25 5 55 nsExternal Clockt CHCX 33 High time 17 t CLCL –t CLCX nst CLCX 33 Low time 17 t CLCL –t CHCX nst CLCH 33 Rise time 5 nst CHCL 33 Fall time 5 nsShift Registert XLXL 32 Serial port clock cycle time 12t CLCL 360 nst QVXH 32 Output data setup to clock rising edge 10t CLCL –133 167 nst XHQX 32 Output data hold after clock rising edge 2t CLCL –80 50 nst XHDX 32 Input data hold after clock rising edge 0 0 nst XHDV 32 Clock rising edge to input data valid 10t CLCL –133 167 nsNOTES:1. Parameters are valid over operating temperature range unless otherwise specified.2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage toPort 0 drivers.4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz.1999 Nov 22 34