LTC6945 - Ultralow Noise and Spurious 0.35GHz to 6GHz Integer-N ...

More documents

Recommendations

Info

LTC6945 PIN FUNCTIONS VREFO + (Pin 1): 3.15V to 3.45V Positive Supply Pin for REFO Circuitry. This pin should be bypassed directly to the ground plane using a 0.1μF ceramic capacitor as close to the pin as possible. REFO (Pin 2): Reference Frequency Output. This produces a low noise square wave, buffered from the REF ± differential inputs. The output is self-biased and must be AC-coupled with a 22nF capacitor. STAT (Pin 3): Status Output. This signal is a configurable logical OR combination of the UNLOK, LOK, THI and TLO status bits, programmable via the STATUS register. See the Operations section for more details. CS (Pin 4): Serial Port Chip Select. This CMOS input initiates a serial port communication burst when driven low, ending the burst when driven back high. See the Operations section for more details. SCLK (Pin 5): Serial Port Clock. This CMOS input clocks serial port input data on its rising edge. See the Operations section for more details. SDI (Pin 6): Serial Port Data Input. The serial port uses this CMOS input for data. See the Operations section for more details. SDO (Pin 7): Serial Port Data Output. This CMOS threestate output presents data from the serial port during a read communication burst. Optionally attach a resistor of >200k to GND to prevent a floating output. See the Operations section for more details. VD + (Pin 8): 3.15V to 3.45V Positive Supply Pin for Serial Port Circuitry. This pin should be bypassed directly to the ground plane using a 0.1μF ceramic capacitor as close to the pin as possible. MUTE (Pin 9): RF Mute. The CMOS active-low input mutes the RF ± differential outputs while maintaining internal bias levels for quick response to de-assertion. GND (Pins 10, 17, 18, 19, 20, 21): Negative Power Supply (Ground). These pins should be tied directly to the ground plane with multiple vias for each pin. 8 RF – , RF + (Pins 11, 12): RF Output Signals. The VCO output divider is buffered and presented differentially on these pins. The outputs are open collector, with 136Ω (typical) pull-up resistors tied to VRF + to aid impedance matching. If used single-ended, the unused output should be terminated to 50Ω. See the Applications Information section for more details on impedance matching. VRF + (Pin 13): 3.15V to 3.45V Positive Supply Pin for RF Circuitry. This pin should be bypassed directly to the ground plane using a 0.01μF ceramic capacitor as close to the pin as possible. BB (Pin 14): RF Reference Bypass. This output must be bypassed with a 1.0μF ceramic capacitor to GND. Do not couple this pin to any other signal. VCO – , VCO + (Pins 15, 16): VCO Input Signals. The differential signal placed on these pins is buffered with a low noise amplifier and fed to the internal output and feedback dividers. These self-biased inputs must be AC-coupled and present a single-ended 121Ω (typical) resistance to aid impedance matching. They may be used singleended by bypassing VCO – to GND with a capacitor. See the Applications Information section for more details on impedance matching. VVCO + (Pin 22): 3.15V to 3.45V Positive Supply Pin for VCO Circuitry. This pin should be bypassed directly to the ground plane using a 0.01μF ceramic capacitor as close to the pin as possible. GND (23): Negative Power Supply (Ground). This pin is attached directly to the die attach paddle (DAP) and should be tied directly to the ground plane. VCP + (Pin 24): 3.15V to 5.25V Positive Supply Pin for Charge Pump Circuitry. This pin should be bypassed directly to the ground plane using a 0.1μF ceramic capacitor as close to the pin as possible. CP (Pin 25): Charge Pump Output. This bi-directional current output is normally connected to the external loop filter. See the Applications Information section for more details. 6945f
PIN FUNCTIONS VREF + (Pin 26): 3.15V to 3.45V Positive Supply Pin for Reference Input Circuitry. This pin should be bypassed directly to the ground plane using a 0.1μF ceramic capacitor as close to the pin as possible. REF + , REF – (Pins 27, 28): Reference Input Signals. This differential input is buffered with a low noise amplifier, which feeds the reference divider and reference buffer. They are self-biased and must be AC-coupled with 470pF BLOCK DIAGRAM 1 V REFO + 2 3 4 5 6 7 8 REFO STAT CS SCLK SDI SDO VD + SERIAL PORT 28 27 REF – REF + 26 VREF + ≤250MHz 9 MUTE R_DIV ÷1 TO 1023 MUTE GND 10 11 RF – 12 RF + LTC6945 capacitors. If used single-ended, bypass REF – to GND with a 470pF capacitor. GND (Exposed Pad Pin 29): Negative Power Supply (Ground). The package exposed pad must be soldered directly to the PCB land. The PCB land pattern should have multiple thermal vias to the ground plane for both low ground inductance and also low thermal resistance. ≤100MHz 350MHz TO 6GHz 13 ÷32 TO 65535 ÷1 TO 6, 50% VRF + PFD LOCK N_DIV O_DIV 24 VCP + BB 14 23 GND CP VVCO + 250μA TO 11.2mA 25 22 350MHz TO 6GHz GND 21 GND 20 GND 19 GND 18 GND 17 VCO 16 15 + VCO – 6945 BD 6945f 9
Page 1 and 2: TYPICAL APPLICATION LTC6945 Ultralo
Page 3 and 4: ELECTRICAL CHARACTERISTICS LTC6945
Page 5 and 6: ELECTRICAL CHARACTERISTICS LTC6945
Page 7: TYPICAL PERFORMANCE CHARACTERISTICS
Page 11 and 12: OPERATION PHASE/FREQUENCY DETECTOR
Page 13 and 14: OPERATION The CPWIDE bit extends th
Page 15 and 16: OPERATION MASTER-CS MASTER-SCLK MAS
Page 17 and 18: OPERATION Table 8. Serial Port Regi
Page 19 and 20: APPLICATIONS INFORMATION 4. Select
Page 21 and 22: APPLICATIONS INFORMATION Choosing t
Page 23 and 24: APPLICATIONS INFORMATION Measured R
Page 25 and 26: APPLICATIONS INFORMATION resistance
Page 27 and 28: PACKAGE DESCRIPTION Please refer to

LTC6945 - Ultralow Noise and Spurious 0.35GHz to 6GHz Integer-N ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?