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<strong>Wafer</strong> level testing<br />
Challenges and opportunities<br />
Scope: CPU + Chipsets<br />
June 3-6, 3<br />
2007<br />
San Diego, CA USA<br />
Vikas Sharma<br />
Manager, <strong>Wafer</strong> test R&D<br />
Intel Corporation
• Moore's Law<br />
Overview<br />
Last<br />
10yrs<br />
Future<br />
Challenges<br />
• <strong>Test</strong> cost prediction from 1990s<br />
• Equipment development impact: CMT<br />
• Current cost projections<br />
• Example of cost reduction through SIU<br />
• Other vectors of test cost<br />
• A word on collaboration<br />
• Summary<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 2
Moore’s s Law: Our friend, our challenge<br />
http://www.intel.com/technology/mooreslaw/index.htm<br />
How to test 2X transistors/2yrs cost-effectively with high quality?<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 3
Recapping the Last 10yrs<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 4
<strong>Test</strong> Cost Trends: Circa 1997<br />
Each generation:<br />
• 2x transistors<br />
test complexity increases<br />
longer test time<br />
Pentium®<br />
processor<br />
• 2x performance<br />
tester speed reqt increases<br />
more expensive testers<br />
Cost metric<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 5
1997 SIA Roadmap – Alarming!<br />
cents /transistor<br />
1<br />
0.1<br />
0.01<br />
0.001<br />
0.0001<br />
0.00001<br />
0.000001<br />
0.0000001<br />
1982<br />
1985<br />
1988<br />
Si manufacturing cost / transistor<br />
<strong>Test</strong> capital / transistor<br />
1991<br />
1994<br />
DFT ATE<br />
‘01 ITRS Roadmap Data<br />
1997<br />
2000<br />
‘97 SIA Roadmap Data<br />
2003<br />
2006<br />
2009<br />
2012<br />
• 1997: Predicted per xtor test cost to exceed fabrication cost<br />
• 2001: DFT & Structural <strong>Test</strong> reduce equipment cost &<br />
complexity<br />
– Lower requirements on I/O data rate, #IO, etc<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 6
1. Developing New <strong>Test</strong>er Architectures<br />
Functional<br />
<strong>Test</strong>ers<br />
Structural<br />
<strong>Test</strong>ers<br />
Configurable<br />
<strong>Test</strong>ers<br />
Next?<br />
<strong>Test</strong>er Cost Metric<br />
<strong>Test</strong>er for<br />
Pentium®<br />
processor<br />
Advancements<br />
in integration<br />
1x<br />
1x 2x 1x 2x<br />
?? 1x 2x 4x<br />
??<br />
• Per site wafer tester is 1/10 of 1995 tester<br />
• Distribute tests. Maximize on cheapest tester<br />
• Introduce methods to confine requirements within tester capability<br />
• Develop equipment for increased performance at lower cost<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 7
Configurable Modular <strong>Test</strong>er (CMT)<br />
and Open Architecture<br />
• Common tester shell with replaceable boards<br />
– True parallel test without any penalty<br />
• Scalable system from commodity through high end<br />
– Adaptable to changing production demands (i.e. CPU, chipsets,<br />
communication products, …)<br />
– Upgradeable as new test technology is developed<br />
Pattern<br />
Gen<br />
Timing<br />
Gen<br />
Pattern<br />
Gen<br />
Timing<br />
Gen<br />
Pattern<br />
Gen<br />
Timing<br />
Gen<br />
Pattern<br />
Gen<br />
Timing<br />
Gen<br />
Pattern<br />
Gen<br />
Timing<br />
Gen<br />
Pattern<br />
Select<br />
Timing<br />
Format<br />
Pattern<br />
Select<br />
Timing<br />
Format<br />
Pattern<br />
Select<br />
Timing<br />
Format<br />
Pattern<br />
Select<br />
Timing<br />
Format<br />
Pattern<br />
Select<br />
Timing<br />
Format<br />
Power<br />
PC<br />
Cooling<br />
Memory:<br />
Scan, Functional<br />
Fail Capture<br />
Clock<br />
Sync<br />
Power<br />
&<br />
Control<br />
Memory:<br />
Scan, Functional<br />
Fail Capture<br />
Clock<br />
Sync<br />
Power<br />
&<br />
Control<br />
Control,Sync,<br />
Data<br />
Memory:<br />
Scan, Functional<br />
Fail Capture<br />
Clock<br />
Sync<br />
Power<br />
&<br />
Control<br />
Memory:<br />
Scan, Functional<br />
Fail Capture<br />
Clock<br />
Sync<br />
Power<br />
&<br />
Control<br />
System BUS<br />
……..<br />
Memory:<br />
Scan, Functional<br />
Fail Capture<br />
Clock<br />
Sync<br />
Power<br />
&<br />
Control<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 8
Intel <strong>Test</strong> Cost Trends Today<br />
Intel® Pentium® Processor<br />
on 350nm <strong>Technology</strong><br />
Intel® Pentium 4® Processor<br />
on 90nm <strong>Technology</strong><br />
1995 - 133MHz<br />
3.3M transistors<br />
2004 - 3.8GHz<br />
125M transistors<br />
Cost metric<br />
65nm<br />
CPU’s<br />
• 65nm CPU’s have >~80x as many transistors<br />
as Pentium® processor but cost less to test<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 9
Cost increase projections<br />
from 1997 were effectively<br />
curbed with cooperative<br />
collaboration on <strong>Test</strong><br />
equipment arch (and DFT)<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 10
But, going forward ….<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 11
Moore’s s Law is Alive and Well<br />
100,000,000,000<br />
10,000,000,000<br />
1,000,000,000<br />
100,000,000<br />
10,000,000<br />
1,000,000<br />
Transistor<br />
Count<br />
1970 1980 1990 2000 2010 2020<br />
100,000<br />
10,000<br />
1,000<br />
Finding the path to 100 Billion transistor devices<br />
Need to reduce test cost/xtor<br />
by ~100X in 10-15yrs<br />
15yrs<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 12
Disturbing trends re-emerging<br />
emerging …<br />
Cost per Transistor (cents)<br />
Log cost/xtor<br />
<strong>Test</strong> cost<br />
Si cost<br />
Flattening<br />
slope?<br />
1980<br />
1982<br />
1984<br />
1986<br />
1988<br />
1990<br />
1992<br />
1994<br />
1996<br />
1998<br />
2000<br />
2002<br />
2004<br />
2006<br />
2008<br />
2010<br />
2012<br />
2014<br />
Need actionable plan to cut cost by 10x in ~5yrs<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 13
Something needs to change ….<br />
<strong>Test</strong> Cost per Unit<br />
90nm 65nm 45nm 32nm<br />
<strong>Test</strong> Cost per Unit<br />
Need actionable plan to cut cost by 10x in ~5yrs<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 14
Tooling >50% <strong>Sort</strong> cost<br />
Deprec.<br />
Labor<br />
<strong>Sort</strong><br />
Tooling (SIU)<br />
SIU costs need to be 1/10 th current costs in ~5yrs<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 15
Technologies with flatter cost<br />
structure desired, and they exist<br />
Old TechA<br />
Cost Metric<br />
Old TechB<br />
New - Large array<br />
New - Small array<br />
#Probes<br />
• Expectation: Lower and relatively flat cost. But, …<br />
• …. Not an order of magnitude reduction. Yet.<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 16
Proof of concept of performance<br />
Pass<br />
Performance<br />
metric<br />
Lifetime (#TD)<br />
• Further development required ….<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 17
Parallelism:<br />
More economical with flatter cost structure<br />
2X<br />
3X<br />
4X<br />
Run rate over 1X<br />
>1.x<br />
>2.x<br />
>>2.x<br />
• Parallelism is worth<br />
pursuing<br />
• Pick optimal level of<br />
parallelism<br />
– Benefits have not scaled<br />
previously because of<br />
disproportionate increase<br />
in SIU cost<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 18
Known Good Die<br />
<strong>Sort</strong> Correlation to Class<br />
OK<br />
(Today)<br />
Probe C4 bumps ????<br />
Excellent<br />
(True KGD)<br />
• Environmental differences a challenge:<br />
– Thermal, electrical (packaging, xIU), content<br />
• Some can be addressed by improved SIU<br />
electrical capabilities<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 19
Other cost levers<br />
• Capital $<br />
– Content<br />
• Do no more testing than required<br />
• Distribute content proactively across sockets.<br />
– Reuse or redefine level of integration in equip<br />
• HC $<br />
– Automation<br />
– Simpler process flow within <strong>Wafer</strong> <strong>Test</strong><br />
– Robust technology<br />
• Reducing need for capital and HC does not<br />
reduce tooling$<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 20
….. And don’t t forget<br />
• Lead time<br />
• Line item agility<br />
FOR Faster response to:<br />
• Rapidly changing customer demand<br />
• Increased WIP velocity in fab<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 21
Needs for next 10-15yrs<br />
15yrs<br />
•Cost<br />
• Lead time<br />
• Agility<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 22
Supplier and customer<br />
collaboration a must to win<br />
• Agree on what to design + fabricate<br />
– Comprehend use condition and<br />
manufacturing requirements<br />
•Make it<br />
• Make it work in required use condition<br />
• Improve<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 23
Summary: Call to Action<br />
• Reduce SIU cost to 1/10 th in ~5yrs<br />
• Collaboration key to achieving<br />
breakthrough results<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 24
Q & A<br />
June 3-6, 3<br />
2007 IEEE SW <strong>Test</strong> Workshop 25
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