E0286 – VLSI Test VLSI Test

E0286 – VLSI Test
Background material on Test:
Test requirements. Test handoffs. Testers.
Where DUT and DFT fit into design / manufacturing framework.
Basic philosophy: Test, ATPG, DFT, BIST, COF, TTR.
Test cost metrics and test economics.

Design and Test Cost Projections
Test cost projections have been possibly
clamped due to better test methods, higher
multi-site, on-die concurrency, etc.
But the percentage cost of test is still
increasing.

Cost of Test
Test
cost
(% of
total
cost)
100%
Design
cost
(% of
total
cost)
50%
Uncertainty
Infrastructure
Fault models
Volume
Logic
30%
50%
1950 1960 1970 1980 1990 2000 2010
Recurring cost of test for 5 (50) seconds of test time is $ 0.05 ($ 0.5)
to $ 0.5 ($ 5.0) @ $ 0.01 to $ 0.1 per second of tester use.

Test Through the Years
Evolution/
Careabouts
Curiosity/
Indifference
1950
Research
labs./Post
design test
University
research
Which
parts
are
bad?
Design for
testability
(DFT)
How
many
bad
parts
have
escaped?
Design for
manufacturability
How
good
are
the
good
parts?
1960 1970 1980 1990 2000 2010 Year

Technology and Failure Modes
Test
complexity
Hookup
tests
Manufacturing
tests / Test
automation
Tests for
better DPPM
screening
Periodic
testing
Board/
External
faults
Stuck-at/
Iddq faults
Layout/
Coupling
faults
Parametric/
Delay faults
Technology scaling / shrinking
Transient
faults

Terminology
- Yield: The entitlement, from the process of good chips, (expressed in %).
- Coverage: Number of faults detected out of the total number of faults that exist,
(expressed in %).
- DPPM: Defective Parts (test escapes) Per Million certified good devices.
Computed for time zero.
- FIT rate: Failures In Time, measured in terms of number of failures in 10^9
hours of operation.
- Reliability: Quantitatively, it can be described using the actual FIT rate.

Terminology (2)
- Defect: This is the actual cause of a fault or failure, e.g. leaky transistor, gate
oxide short, etc.
- Fault / Failure: This is the effect, e.g. high Iddq, gate output stuck-at 0, etc.
- Errors: This is the manifestation of the fault at an observable output.
- Outlier: Devices for which parametric measurements do not conform to an
acceptable deviation around the mean.

Few Decades of Test
q 1950s - Gedankan experiments.
University
q 1960s - D-algebra.
q 1970s - LSSD and scan design.
Design Groups
q 1980s - DFT. Early automation.
q 1990s - Automation for DFT insertion and pattern generation.
CAD Groups
q 2000s - DFM. DFY. Cost / Quality tradeoffs.
q 2010s - ... .

Interesting Test Data
Reliability / DPPM control:
- 0% fault coverage -> 100% yield.
- > 99% stuck-at fault coverage at 75% yield for DPPM < 200.
- But likely DPPM > 200. Confidence in yield low.
- DPPM requirements for several products in the100s, 10s and 1s range.
- 0.5% yield -> DPPM of 5000.
Test cost:
- Cost of test vs design. Crossover in a few years.
- Cost of logic inside device vs outside.
- Rule of 10s: $1 in device -> $1000+ on field.
- Cost impact: Few seconds to tens of seconds.
- Cost per second: 2 to 10 cents. Infrastructure extra.

Interesting Test Data (2)
Design effort towards DFT:
- From 10% to 40%.
-Variation depending upon nature of IP cores and SOC, extent of re-use, etc.
Time to production:
- Design time: Months.
- Test screening / Ramp to production: Also months.
- Fail Pass iterations: Costly. Result in longer manufacturing cycles and
increased time to ramp to volume.
SOCs designs and DSM (deep sub-micron) effects together aggravate problems
in each of the above.

Components of Test Cost
Design costs - primary and derived:
- Area, test generation time, etc.
- Cost of attaining coverage, performance, etc.
Test infrastructure costs:
- Test automation tools
- Test program creation.
- Test volume. Test application time.
- Probe cards, boards and accessories.
- Tester time.
Test technology costs:
- Capabilities for test screening and debug.
- Impact on design and infrastructure.

Cost of Testing
CPUD = ( CTGD + CTBD ) / (TNOD * Y)
CPUD = Cost per unit die.
CTGD = Cost of testing good dies.
CTBD = Cost of testing bad dies. (May be = CTGD in multi-site context).
TNOD = Total number of dies.
Y = Yield.

Cost of Testing (2)
Cw = Wafer cost.
D = Dies per wafer.
Y = Test yield.
Tg
= Test time taken to test a good part.
Tb = Average time it takes for a bad part to fail.
Ctu = Tester time cost per unit time.
Test time per wafer (Tt) = [D * Y * Tg] + [D * (1-Y) * Tb]
Test cost per wafer (Ct) = Ctu * Tt
Test cost per good die (Ctg) = Ct / (D * Y)
= Ctu {Tg
+ Tb * [1/Y –1]}
Fabrication cost per good die (Cwg) = Cw / (D * Y)
Test cost -> Add costs across different tests / testers.

Cost Tradeoffs – Example 1
Trade off coverage with effectiveness.
Select tests based on their effectiveness.
- Test A, Efficiency = 80%, Coverage = 90%.
- Test B, Efficiency = 90%, Coverage = 95%.
- Test C, Efficiency = 70%, Coverage = 100%.
Selection of A + B is more effective than B + C.
0.9*0.95 + 0.8*0.9 > 0.9*0.95 + 0.7+1.0

Cost Tradeoffs – Example 2
Reduce the time taken for the bad parts to fail. Order the tests based on their
efficiency.
- Test A, Yield = 80% (less coverage), Time = 7ms.
- Test B, Yield = 60% (more coverage), Time = 8ms.
Test A followed by Test B:
Total test time = 7 ms + 8x0.8 ms = 13.4 ms.
Test B followed by Test A:
Total test time = 8 ms + 7x0.6 ms = 12.2 ms

Reducing Cost of Testing
- Target tests on cheaper testers:
- Application costs: $0.01/sec to 0.1/sec and above.
- Actual costs: $ 0.2 M to $ 2 M and above.
- Multi-site testing. Concurrent testing.
- Reduce dependency on tester infrastructure.
- Increase / Reduce the test application speed.
- Improve quality of tests for a given cost. Trade off coverage with quality.
- Test sequence: Bad parts to fail early.
- Incur DFT overhead. (Parallel scan, faster scan, test points, BIST, test modes,
isolation, etc.).

Apportioned Test Cost
700000
Cost
600000
500000
400000
300000
200000
Test time - 1
Die DFT
Tester PE
Tester HW - 1
Tools DFT
Design DFT - 1
100000
0
1 2 3
4 5 6
Time

Product Life-time Cost
3000000
Cost
2500000
2000000
1500000
1000000
Test time - 1
Die DFT
Tester PE
Tester HW - 1
Tools DFT
Design DFT - 1
500000
0
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
Time

Diverse Markets
q Designs spec’ed and created for one market re-used for others. Examples:
¦ Catalogue wireless connectivity chips re-used inside cars / planes.
¦ DSPs re-used for automotive engine control.
¦ Micro-contollers for medical applications.
q Quality is an opportunity cost. Price paid to meet vs price incurred not to.
Parameter Catalog Portable Infrastructure Automotive
Coverage
Time Zero Quality
Field DPPM
Test Cost
Test Power
Performance
Area

Apportioned Quality Cost
700000
Cost
600000
500000
Test time - 2
Tester HW - 2
400000
Design DFT - 2
Test time - 1
300000
Die DFT
Tester PE
200000
Tester HW - 1
Tools DFT
100000
Design DFT - 1
0
1 2 3
4 5 6
Time

Apportioned Quality Cost (2)
3500000
Cost
3000000
2500000
Test time - 2
Tester HW - 2
2000000
Design DFT - 2
Test time - 1
1500000
Die DFT
Tester PE
1000000
Tester HW - 1
Tools DFT
Design DFT - 1
500000
0
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
Time

Different Techniques Beyond Production Test
Techniques
Technology: Cell hardening.
Physical design rules.
Margins: Additional design margins.
Margin mode testing.
DFT partitioning:
Scan partitioning. Clock skewing / staggering. Test res.part. x x
ATPG: Parametric tests. Defect based tests. Bus BIST. x x
Power aware test.
Power management: Power grid partitioning / over-design.
Power isolation switches. Retention.
x x
x
Device configurability:
Pre-shipment calibration. Memory repair. Module isolation. x
On-chip test / measurement:
Self-test. Self-calibration. Self-repair. Adaptivity.
Die test: Over-test. Stress test.
Under-test. Binning. Adaptive test.
System test:
Field test. Periodic testing.
Tolerance: Error checking and correction.
Redundancy and reconfiguration.
Yield Reliability Power
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

How Coverage Impacts Fall-out
Reject rate
4500
4000
3500
3000
2500
2000
1500
1000
500
Will Brown
Seth Ag 1.5
Seth Ag 1.8
Seth Ag 2.0
Seth Ag 2.5
DSP empirical
The formulae are a
guide. Deviations exist
for different reasons.
0
55% 60% 65% 70% 75% 80% 85% 90% 95% 100%
Stuck-at Test Coverage

Importance of DPPM
- Theoretical example:
- Sample of 10^6 devices.
- 10000 are faulty.
- 100 escape manufacturing test screen.
- Yield = 99%. DPPM = 100.
- Coverage = 99%, (assuming equal distribution and occurrence of modelled
faults).
- Practical case:
- Yield much lower. More faulty devices.
- Coverage much lower. More test escapes.
- Modelled faults do not occur uniformly.
- Several non-modelled faults also occur.
- Beta quality of silicon test program.
- Result: DPPM of 10000s. On ramp, DPPM of 100s.

Impact of Non-zero DPPM
Consider a board with ten devices, each with DPPM of 1000:
- The DPPM of this board is 10000, i.e. 1%.
- One in hundred boards is bad.
Consider an automobile with 100 devices, each with DPPM of 100:
- The DPPM of this automobile system, (chips alone,other systems apart), is
10000, i.e. 1%.
- One in hundred automobiles is bad.
Consider an automobile with 100 devices, each with DPPM of 1:
- The DPPM of this automobile system is 100, i.e. 0.01%. One in ten
thousand automobiles is bad.

DPPM Calculation
The Williams and Brown equation relates the escape rate (DPPM) to the fault
coverage for a given yield.
D = (1 - Y^(1-C)), where
Y = Yield, 0

IP Mixture in SOC
H
A
C
D
E
B
F
G
Core A: No compression. No bounding. E: Glue logic.
Core B: No compression. Bounding only. G: SOC level CoDec(s).
Core C: Compression + Bounding
H: SOC bounding.
Core D: Compression only. No bounding. Bounding.
F: DFT logic
• Test IPs – Memory BIST,
scan CoDecs, test mode
controls, E-Fuse, etc.
• Wrappers – Pin-muxing,
analog PMT, 1500 bounding,
etc.

Test Scheduling Options
Schedule
C -> D -> G(A+B+E) -> F
C -> [Init(A+E) + Init(B) + Init(C) -> D]* -> G(A+B) -> E -> F
C -> [Init(C) -> Init(E) -> [G(A+B) || D]* -> E -> F
C || G(A+B+E) || D -> F
Test Time
Test Qual
H
A
C
D
E
B
F
G

Test Data Volume Required to Test DUT
Pattern Count
31000
29000
27000
25000
23000
21000
19000
17000
15000
Patterns
0 250 500 750 1000 1250 1500 1750
TDV per Pattern
The product of X-Y co-ordinate values is not constant. DUT test
entropy drives CoDec selection and QOR. Test data meeting
entropy requirements ensures higher coverage.

Generic Self-test Controller
External host
or interface
Self-test
microcode
Internal memory
(self-test config.)
Read
Master CPU
DUT with scan
compression +
DUT
addl. control
BIST
Write
Status
registers
Possibilities: (i) One-time manufacturing
test. (ii) Fixed time field test. (iii)
Periodic field test. (iv) Online test
concurrent with normal operation.
Normal appl.
time slot
Test
application
A1 T1 A2 T2 A3 T3 A4

Scatter Plots – How to Distinguish between Good and Bad
Normalized Fmax
Process Spread
Process spread

Illustration: Variability DPPM
q Variability DPPM : Fails intermittently at

Coverage Improvements Across Fault Models
Coverage
Hybrid ATPG
FM1
FM2
Stuck-at
Transition
Path delay
Bridging
Pattern Count
Methodology
q TC1(FM1) + TC2(FM2) vs defect coverage.
q Pattern sets: P1 + P2 versus merged set of
patterns.
Optimized Pattern Set

Cost versus Coverage
Test
cost
Fixed test cost
Test A
Test B
Defect coverage
Move to more effective tests B, e.g. transition, bridging, etc.

Cost versus Quality Tradeoffs
Quality
Required
quality
Benefit
of test
Unacceptable
quality
Process capability
Test allows use of inherently low quality process to manufacture devices
with high quality levels. Yield loss is made up for by increased competitiveness.

Bath-tub Curve
Extrinsic / Latent
defects
Intrinsic failures /
Ageing
Product
Eval.
Device Eval

Test Components under Multi-site
q Test 1: 200 ms.
Die IP Type of Test
MS
Factor
q Tests 2 to N: Less than 20 ms.
X1 X16 X16 ->
X64
X16 ->
X128
Option 1 220 ms 14 ms NA NA
Option 2 220 ms 1.5 ms 4.5 ms NA
Option 3 SKIP 1.5 ms SKIP 3.25 ms
Single Single Single site
Single Multiple (same) Single site
Single Multiple (different) Single site
Multiple (same) Single Multi-site
Multiple (same) Multiple (same) Multi-site
Multiple (same) Multiple (different) Multi-site
Multiple (different) Single Non-identical
Multiple (different) Multiple (same) Non-identical
Multiple (different) Multiple (different) Non-identical
Multiple insertions required.
Test content varies in different insertions.
Selection of test content, test concurrency and multi-site factor important.

Tester Board

Test Power Concerns
Normalized
Power
15
10
5
0
5.2X
Video
Decode
1.7X
Test (Pre-
Opt) *
Test (with
Opt)
Test power can be several times
more than normal mode power
Peak test power issues (IR drop issues)
impact yield
Affects both shift and capture operations.

Distinguishing Good Parts – An Analog Process
Good / Perfect
Part
SPECIFICATION
/ FEATURE
TEST
• Defect free.
• Identification elusive.
• Costly.
Acceptable
Part
FUNCTIONAL
TEST
• Error free.
• Used in speed binning.
• Often enabled through
outlier analysis.
• May need Schmoo data.
• Parametric defects
targetted.
• Targetted tests: Iddq, path
delay, DFT R/W controls,
DC parametrics,
functional, etc.
Bad Part
DEFECT
ORIENTED TEST
• Static defects targetted.
• Gross errors assumed.
• Targetted tests: Stuck-at,
transition, small delay
defect, bridging, memory
algorithmic tests, etc.
• Successful created,
adopted, optimised,
adapted.

Four Quadrant Analysis
II
I
Built-in Self Tests
(Structural)
BAD GOOD
Underkill
Yield Loss
III
IV
Units to Ship
Overkill
BAD
GOOD
Traditional Tests
(Functional, Parametric, …)

Test Effectiveness Using Venn Diagrams
42

Thank you.