Automotive Innovators Hit High Gear in - Xilinx

XCELLENCE IN AUTOMOTIVE & ISM
sync _ inp
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in 0
in 1
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in 8
synch counter and reset
for the memory addressing, some simple
binary logic and registers to implement
appropriate delays.
The blue shading and the Xilinx logo
indicate the System Generator primitive
blocks, each of which corresponds to optimized
synthesizable HDL code. Through
this graphical interface, System Generator
allows the algorithm developer to easily
implement a DSP algorithm in hardware
without having any knowledge of HDL
coding techniques.
We use the second main subsystem, the
5x5 FIR kernel (shown in blue in Figure 3),
to implement the convolution operation. It
receives in input a block of 25 pixels from
the line buffer block, multiplies them by the
25 coefficients of the Gaussian mask and
accumulates the result into a register. We
show the details of the implementation in
Figure 5. To fit the performance of the tar-
sync
In 1
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counter
reset _out
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4 tapsdelay 1
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4 tapsdelay 2
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In 1
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4 tapsdelay 3
out
mux 9 A
(latency =2)
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addr z -2
ROM A
addr z -2
ROM B
addr z -2
ROM C
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Delay 2
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3 mux 9 (latency = 2 )
sel
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
in 8
out
mux 9 B
(latency =2)
2
Out B
Sel
Sel
Sel
z -3
Delay 3
coeff _from _rom
mux _out
DSP 48 Macro (latency = 4 ) A
coeff _from _rom
mux _out
DSP 48 Macro (latency = 4 ) B
coeff _from _rom
mux _out
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d
en
d
en
d
en
z q -1
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z q -1
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mux 9 C
latency =3
out
get device and to achieve a specified sample
rate of 9 million samples per second
(MSPS), we chose to use three multiplyaccumulators
(which we implemented using
the FPGA’s DSP48 programmable Multiply
Accumulator functional units) in parallel.
We dedicated each of them, at most, to nine
multiplications, via time-division multiplexing
(see the larger System Generator blocks
in the top diagram of Figure 5). We split and
stored the set of 25 coefficients of the mask
in three ROMs that we implemented as distributed
RAM (another memory resource
the FPGA provides).
In our implementation, we chose to fix
the coefficients of the mask at compile time.
However, we could have easily updated the
design to accept these values as real-time
inputs. In this way we could dynamically
change the run-time intensity of the filtering
based on environmental conditions.
(Implementation Note: Because of the
isotropic shape of the Gaussian, the kernel
could be decomposed in two separable
masks and the filtering could be obtained as
two consecutive convolutions with 1x5 and
5x1 masks along the horizontal and vertical
directions. Even though this approach
would reduce the FPGA resources required,
we didn’t adopt it to avoid losing generality
and readability of the design.)
Another powerful feature found in
System Generator is the ability to apply a
preload MATLAB function to customize
the design before compilation. By setting
parameters of the System Generator module
(such as image resolution, FIR kernel
values and the number of computational
precision bits) and initializing the workspace
signals we used during the run-time
simulation, we can quickly and easily
experiment with different processing
24 Xcell Journal Fourth Quarter 2008
3
Out C
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z -1
Down Sample
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Down Sample 1
↓9
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Down Sample 2
Figure 5 – System Generator implementation
of FIR (convolution) filter
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Convert 1
1
filtered
[a:b]
Slice 1
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Slice
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in 0
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in 1
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in 4
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