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Automotive Innovators Hit High Gear in - Xilinx

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XPERIMENT<br />

Now that I had a work<strong>in</strong>g hardware platform, it was time to write some code.<br />

I downloaded and <strong>in</strong>stalled ISE from the Xil<strong>in</strong>x site and got the USB<br />

<strong>in</strong>terface up and runn<strong>in</strong>g so I could program the Spartan-3.<br />

those six controls had to be operated under<br />

computer control.<br />

I disassembled the guitar body and<br />

poked around until I figured out which pads<br />

on the circuit board were driven by the various<br />

buttons. Six bits from the comput<strong>in</strong>g<br />

platform drove an LS244 with current-limit<strong>in</strong>g<br />

resistors on the outputs. Optoisolators<br />

(see Figure 3) mounted on a small circuit<br />

board <strong>in</strong>side the guitar body drove each of<br />

the button pads. The comput<strong>in</strong>g platform<br />

and guitar body are connected together<br />

through a n<strong>in</strong>e-conductor RS232 cable.<br />

Challenge No. 3: Hav<strong>in</strong>g the analog section<br />

and I/O prototyped and debugged,<br />

my thoughts turned to pick<strong>in</strong>g the right<br />

comput<strong>in</strong>g platform. S<strong>in</strong>ce I was an FPGA<br />

novice, it had to be reasonably simple, really<br />

fast, really powerful, have a stable programm<strong>in</strong>g<br />

environment and should be<br />

someth<strong>in</strong>g I could grow <strong>in</strong>to and learn<br />

from. That’s when I found Digilent.<br />

Digilent is a great company, and they<br />

offer a Spartan-3 ®-based FPGA demo<br />

board that I thought would be perfect for<br />

the application. In fact, there are so many<br />

gates and so much I/O that I knew the<br />

board would be overkill—but as with all<br />

comput<strong>in</strong>g platforms today, you get a lot of<br />

bang for the buck.<br />

Challenge No. 4: A small matter of programm<strong>in</strong>g<br />

the system. Now that I had a<br />

work<strong>in</strong>g hardware platform, it was time to<br />

write some code (Figure 4). I downloaded<br />

and <strong>in</strong>stalled ISE ® from the Xil<strong>in</strong>x site and<br />

got the USB <strong>in</strong>terface up and runn<strong>in</strong>g so I<br />

could program the Spartan-3. There’s a<br />

pretty steep learn<strong>in</strong>g curve before you can<br />

do anyth<strong>in</strong>g useful, but once you get your<br />

head around the idea of design<strong>in</strong>g with<br />

gates, it’s <strong>in</strong>credibly powerful.<br />

In the microprocessor world, everyth<strong>in</strong>g<br />

happens sequentially. Set up this variable. Do<br />

this. Do this next. Then do this. If this happens,<br />

do someth<strong>in</strong>g else. It’s systematic and<br />

progressive, and tim<strong>in</strong>g is important. “How<br />

long does it take to go through this loop?”<br />

The world of programmable logic is different.<br />

Everyth<strong>in</strong>g happens <strong>in</strong> parallel—and<br />

at almost wire speed. No count<strong>in</strong>g clock<br />

cycles. Everyth<strong>in</strong>g just occurs at the same<br />

time. If you need a 13-bit counter, you write<br />

a l<strong>in</strong>e of code. If you need a six-<strong>in</strong>put gate,<br />

you write a l<strong>in</strong>e of code. It’s fantastic, like<br />

reach<strong>in</strong>g <strong>in</strong>to a magical junk box and pull<strong>in</strong>g<br />

out the perfect part. Need to build a divideby-50<br />

million counter? Instead of wire-wrapp<strong>in</strong>g<br />

p<strong>in</strong> after p<strong>in</strong> to make one, just write a<br />

l<strong>in</strong>e of code. Didn’t get it right? No need for<br />

an unwrap tool—just rewrite the l<strong>in</strong>e.<br />

For <strong>in</strong>stance, here’s the VHDL code to<br />

set up two counters:<br />

signal l<strong>in</strong>e_cnt:std_logic_vector(8<br />

downto 0);9 bit counter 0 to 511<br />

signal samp_cnt:std_logic_vector(12<br />

downto 0);13 bit counter 0 to 8191<br />

Now, take a look at the VHDL code to<br />

count l<strong>in</strong>es. It counts from 0 to 262 and<br />

then resets to zero each time vertical sync<br />

gets asserted:<br />

process(v_sync, burst, l<strong>in</strong>e_cnt)<br />

beg<strong>in</strong><br />

if burst'event and burst = '0'then<br />

if v_sync = '0' then<br />

l<strong>in</strong>e_cnt

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