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Xilinx ISE Simulator (ISim) In-Depth Tutorial

Xilinx ISE Simulator (ISim) In-Depth Tutorial

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Chapter 4: Using the <strong>ISim</strong> Graphical User <strong>In</strong>terface<br />

Note: Divider names can be changed at any time by double-clicking on the divider name or pressing<br />

the F2 function key, and entering a new name.<br />

Your Wave window should be similar to the one shown in Figure 4-18 (with Groups<br />

collapsed).<br />

X-Ref Target - Figure 4-18<br />

Adding Signals from Sub-Modules<br />

Figure 4-18: Adding Dividers<br />

You will now add signals from the instantiated DCM module (<strong>In</strong>st_drp_dcm) and the<br />

instantiated DRP controller module (<strong>In</strong>st_drp_statmach) in order to study the<br />

interactions between these sub-modules and the test bench test signals.<br />

Follow these steps to add the necessary signals:<br />

1. <strong>In</strong> the <strong>In</strong>stances and Processes panel, expand the hierarchy by clicking once to the left<br />

of each child module (refer to Figure 4-19).<br />

2. Simulation objects associated with the currently highlighted design unit will appear in<br />

the Objects panel (refer to Figure 4-20).<br />

42 www.xilinx.com <strong>ISE</strong> <strong>ISim</strong> <strong>In</strong>-<strong>Depth</strong> <strong>Tutorial</strong><br />

UG682 (v 12.3) September 21, 2010

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