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skew is the deviation from this ideal time delay. I/Q PN chip skew is defined in Figure
E-17.
Data
Level
I
Channel
Q
Channel
0.5T c 1T c 1.5T c 2T c 2.5T c 3T c 3.5T c 6.5T c
Figure E-17. Definition of I/Q PN Code Chip Skew
E.18.2 Command/Range Channel PN Chip Skew
The ideal time delay between the chip transitions on the command channel and the chip
transitions on the range channel is zero. The command/range channel PN chip skew is
the deviation from this ideal time delay.
E.19 PN Chip Asymmetry
PN chip asymmetry is defined as follows:
length of long chip - length of short chip
length of long chip + length of short chip
100%
E.20 PN Chip Jitter
PN code chip jitter is defined as the unwanted phase variations of the PN code chip
clock measured in degrees rms. A PN code chip clock with PN code chip jitter can be
expressed as follows:
c( t)
sgncos(
2f
pnt
(
t)
where
f pn desired PN code chip rate in Hz
4T c 4.5T c 5T c 5.5T c 6T c 7T c 7.5T c 8Tc
(t)
PN code chip clock phase jitter in radians
The PN code chip jitter is the rms value of (t)
expressed in degrees.
Revision 10 E-12 450-SNUG
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