C8051F326/7 - Silicon Labs

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<strong>C8051F326</strong>/7 SFR Definition 13.5. SBRLH0: UART0 Baud Rate Generator High Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-0: SBRLH0[7:0]: High Byte of reload value for UART0 Baud Rate Generator. SFR Definition 13.6. SBRLL0: UART0 Baud Rate Generator Low Byte Bits7-0: SBRLL0[7:0]: Low Byte of reload value for UART0 Baud Rate Generator. 126 Rev. 1.1 SFR Address: 0x94 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x93
14. Timers <strong>C8051F326</strong>/7 Each MCU includes two 16-bit timers compatible with those found in the standard 8051. These timers can be used to measure time intervals and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Table 14.1. Timer Modes Timer 0 and Timer 1 Modes: 13-bit timer 16-bit timer 8-bit timer with auto-reload Two 8-bit timers (Timer 0 only) Timers 0 and 1 may be clocked by one of four sources, determined by the Timer Mode Select bits (T1M- T0M) and the Clock Scale bits (SCA1-SCA0). The Clock Scale bits define a pre-scaled clock from which Timer 0 and/or Timer 1 may be clocked (See Figure 14.3 for pre-scaled clock selection). Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timers 0 and 1 have a gate mode which allows the timer to run only when an external interrupt is active (/INT0 for Timer 0 and /INT1 for Timer 1. This mode facilitates pulse width measurements on input on P0.2 (Timer 0) and Low Frequency oscillator calibration when used with Timer 1. 14.1. Timer 0 and Timer 1 Operating Modes Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Timer Control register (TCON) is used to enable Timer 0 and Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register (Section “6.3.5. Interrupt Register Descriptions” on page 50); Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register (SFR Definition 6.7). Both timers operate in one of four primary modes selected by setting the Mode Select bits T1M1-T0M0 in the Timer Mode register (TMOD). Each timer can be configured independently. Each operating mode is described below. Rev. 1.1 127
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USB Function Controller - USB speci
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Table of Contents C8051F326/7 1. Sy
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C8051F326/7 12.12.Controlling Endpo
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List of Figures C8051F326/7 1. Syst
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List of Tables C8051F326/7 1. Syste
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List of Registers C8051F326/7 SFR D
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1. System Overview C8051F326/7 C805
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REGIN VDD GND /RST/C2CK D+ D- VBUS
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1.1. CIP-51 Microcontroller Core 1.
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1.2. On-Chip Memory C8051F326/7 The
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1.5. On-Chip Debug Circuitry C8051F
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2. Absolute Maximum Ratings Table 2
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4. Pinout and Package Definitions N
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P0.0 GND D+ D- VIO VDD REGIN 1 2 3
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Figure 4.3. QFN-28 Package Drawing
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5. Voltage Regulator (REG0) C8051F3
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From VBUS From 3 V Power Net VBUS R
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6. CIP-51 Microcontroller C8051F326
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6.1.2. MOVX Instruction and Program
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Table 6.1. CIP-51 Instruction Set S
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6.2. Memory Organization C8051F326/
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6.2.6. Special Function Registers C
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6.2.7. Register Descriptions C8051F
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SFR Definition 6.6. B: B Register C
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6.3.2. External Interrupts C8051F32
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SFR Definition 6.7. IE: Interrupt E
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SFR Definition 6.9. EIE1: Extended
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6.4. Power Management Modes C8051F3
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7. Reset Sources C8051F326/7 Reset
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7.2. Power-Fail Reset / VDD Monitor
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SFR Definition 7.2. RSTSRC: Reset S
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8. Flash Memory C8051F326/7 On-chip
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8.2. Non-volatile Data Storage C805
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SFR Definition 8.2. FLKEY: Flash Lo
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9. External RAM C8051F326/7 The C80
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10. Oscillators C8051F326/7 C8051F3
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SFR Definition 10.2. OSCICL: Intern
Page 75 and 76: 10.4. 4x Clock Multiplier C8051F326
Page 77 and 78: SFR Definition 10.5. CLKSEL: Clock
Page 79 and 80: 11. Port Input/Output C8051F326/7 O
Page 81 and 82: 11.1. Port I/O Initialization Port
Page 83 and 84: SFR Definition 11.4. P2: Port2 Bits
Page 85 and 86: Table 11.1. Port I/O DC Electrical
Page 87 and 88: 12. Universal Serial Bus Controller
Page 89 and 90: C8051F326/7 USB Register Definition
Page 93 and 94: USB Register Name Table 12.2. USB0
Page 95 and 96: 12.5. FIFO Management C8051F326/7 2
Page 97 and 98: 12.6. Function Addressing C8051F326
Page 99 and 100: USB Register Definition 12.8. POWER
Page 101 and 102: 12.8. Interrupts C8051F326/7 The re
Page 105 and 106: 12.10.2.Endpoint0 IN Transactions C
Page 109 and 110: C8051F326/7 Hardware will automatic
Page 115 and 116: Table 12.4. USB Transceiver Electri
Page 117 and 118: 13. UART0 C8051F326/7 UART0 is an a
Page 119 and 120: BRG Clock = 12 MHz BRG Clock = 24 M
Page 121 and 122: 13.3. Configuration and Operation C
Page 123 and 124: SFR Definition 13.1. SCON0: UART0 C
Page 125: SFR Definition 13.3. SBUF0: UART0 D
Page 129 and 130: 14.1.2. Mode 1: 16-bit Timer C8051F
Page 131 and 132: SFR Definition 14.1. TCON: Timer Co
Page 133 and 134: SFR Definition 14.3. CKCON: Clock C
Page 135 and 136: 15. C2 Interface C8051F326/7 C8051F
Page 137 and 138: 15.2. C2 Pin Sharing C8051F326/7 Th
Page 139 and 140: NOTES: C8051F326/7 Rev. 1.1 139
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C8051F326/7 - Silicon Labs

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