C8051F326/7 - Silicon Labs

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<strong>C8051F326</strong>/7 SFR Definition 14.2. TMOD: Timer Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value GATE1 Reserved T1M1 T1M0 GATE0 Reserved T0M1 T0M0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x89 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. /INT1 is activated when the internal oscillator resumes from a suspended state. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active. /INT1 is activated every 2 low frequency oscillator clock cycles. This is a rate of 40kHz. Bit6: Reserved. Read = 0b. Must write 0b. Bits5–4: T1M1-T1M0: Timer 1 Mode Select. These bits select the Timer 1 operation mode. T1M1 T1M0 Mode 0 0 Mode 0: 13-bit timer 0 1 Mode 1: 16-bit timer 1 0 Mode 2: 8-bit timer with auto-reload 1 1 Mode 3: Timer 1 inactive Bit3: GATE0: Timer 0 Gate Control. 0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level. /INT0 input pin is P0.0. 1: Timer 0 enabled only when TR0 = 1 AND /INT0 is active. /INT0 input pin is P0.2. Bit2: Reserved. Read = 0b. Must write 0b. Bits1–0: T0M1-T0M0: Timer 0 Mode Select. These bits select the Timer 0 operation mode. T0M1 T0M0 Mode 0 0 Mode 0: 13-bit timer 0 1 Mode 1: 16-bit timer 1 0 Mode 2: 8-bit timer with auto-reload 1 1 Mode 3: Two 8-bit timers 132 Rev. 1.1
SFR Definition 14.3. CKCON: Clock Control <strong>C8051F326</strong>/7 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value — — — — T1M T0M SCA1 SCA0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8E Bit7–4: Unused. Read = 0b. Write = don’t care. Bit3: T1M: Timer 1 Clock Select. This select the clock source supplied to Timer 1. 0: Timer 1 uses the clock defined by the prescale bits, SCA1-SCA0. 1: Timer 1 uses the system clock. Bit2: T0M: Timer 0 Clock Select. This bit selects the clock source supplied to Timer 0. 0: Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0. 1: Timer 0 uses the system clock. Bits1–0: SCA1-SCA0: Timer 0/1 Prescale Bits. These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured to use prescaled clock inputs. SCA1 SCA0 Prescaled Clock 0 0 System clock divided by 12 0 1 System clock divided by 4 1 0 System clock divided by 48 Note: External clock divided by 8 is synchronized with the system clock. Rev. 1.1 133
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USB Function Controller - USB speci
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Table of Contents C8051F326/7 1. Sy
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C8051F326/7 12.12.Controlling Endpo
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List of Figures C8051F326/7 1. Syst
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List of Tables C8051F326/7 1. Syste
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List of Registers C8051F326/7 SFR D
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1. System Overview C8051F326/7 C805
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REGIN VDD GND /RST/C2CK D+ D- VBUS
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1.1. CIP-51 Microcontroller Core 1.
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1.2. On-Chip Memory C8051F326/7 The
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1.5. On-Chip Debug Circuitry C8051F
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2. Absolute Maximum Ratings Table 2
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4. Pinout and Package Definitions N
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P0.0 GND D+ D- VIO VDD REGIN 1 2 3
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Figure 4.3. QFN-28 Package Drawing
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5. Voltage Regulator (REG0) C8051F3
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From VBUS From 3 V Power Net VBUS R
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6. CIP-51 Microcontroller C8051F326
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6.1.2. MOVX Instruction and Program
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Table 6.1. CIP-51 Instruction Set S
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6.2. Memory Organization C8051F326/
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6.2.6. Special Function Registers C
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6.2.7. Register Descriptions C8051F
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SFR Definition 6.6. B: B Register C
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6.3.2. External Interrupts C8051F32
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SFR Definition 6.7. IE: Interrupt E
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SFR Definition 6.9. EIE1: Extended
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6.4. Power Management Modes C8051F3
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7. Reset Sources C8051F326/7 Reset
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7.2. Power-Fail Reset / VDD Monitor
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SFR Definition 7.2. RSTSRC: Reset S
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8. Flash Memory C8051F326/7 On-chip
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8.2. Non-volatile Data Storage C805
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SFR Definition 8.2. FLKEY: Flash Lo
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9. External RAM C8051F326/7 The C80
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10. Oscillators C8051F326/7 C8051F3
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SFR Definition 10.2. OSCICL: Intern
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10.4. 4x Clock Multiplier C8051F326
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SFR Definition 10.5. CLKSEL: Clock
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11. Port Input/Output C8051F326/7 O
Page 81 and 82: 11.1. Port I/O Initialization Port
Page 83 and 84: SFR Definition 11.4. P2: Port2 Bits
Page 85 and 86: Table 11.1. Port I/O DC Electrical
Page 87 and 88: 12. Universal Serial Bus Controller
Page 89 and 90: C8051F326/7 USB Register Definition
Page 93 and 94: USB Register Name Table 12.2. USB0
Page 95 and 96: 12.5. FIFO Management C8051F326/7 2
Page 97 and 98: 12.6. Function Addressing C8051F326
Page 99 and 100: USB Register Definition 12.8. POWER
Page 101 and 102: 12.8. Interrupts C8051F326/7 The re
Page 105 and 106: 12.10.2.Endpoint0 IN Transactions C
Page 109 and 110: C8051F326/7 Hardware will automatic
Page 115 and 116: Table 12.4. USB Transceiver Electri
Page 117 and 118: 13. UART0 C8051F326/7 UART0 is an a
Page 119 and 120: BRG Clock = 12 MHz BRG Clock = 24 M
Page 121 and 122: 13.3. Configuration and Operation C
Page 123 and 124: SFR Definition 13.1. SCON0: UART0 C
Page 125 and 126: SFR Definition 13.3. SBUF0: UART0 D
Page 127 and 128: 14. Timers C8051F326/7 Each MCU inc
Page 129 and 130: 14.1.2. Mode 1: 16-bit Timer C8051F
Page 131: SFR Definition 14.1. TCON: Timer Co
Page 135 and 136: 15. C2 Interface C8051F326/7 C8051F
Page 137 and 138: 15.2. C2 Pin Sharing C8051F326/7 Th
Page 139 and 140: NOTES: C8051F326/7 Rev. 1.1 139
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C8051F326/7 - Silicon Labs

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