08.06.2013 Views

C8051F326/7 - Silicon Labs

C8051F326/7 - Silicon Labs

C8051F326/7 - Silicon Labs

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

REGIN<br />

VDD<br />

GND<br />

/RST/C2CK<br />

D+<br />

D-<br />

VBUS<br />

XTAL2<br />

Analog/Digital<br />

Power<br />

C2D<br />

Low Freq<br />

Oscillator<br />

12 MHz<br />

Internal<br />

Oscillator<br />

Clock<br />

Recovery<br />

5.0 V Voltage<br />

IN<br />

Regulator<br />

OUT<br />

POR<br />

Debug HW<br />

Brown-<br />

Out<br />

x4 2<br />

1,2,3,4<br />

2<br />

XTAL2<br />

USB<br />

Transceiver<br />

Enable<br />

USB Clock<br />

Reset<br />

System<br />

Clock<br />

USB<br />

Controller<br />

256 byte<br />

USB SRAM<br />

8<br />

0<br />

5<br />

1<br />

C<br />

o<br />

r<br />

e<br />

16 kB<br />

FLASH<br />

256 byte<br />

SRAM<br />

1 kB<br />

XRAM<br />

SFR Bus<br />

Port 0<br />

Latch<br />

UART<br />

/SYSCLK<br />

Timer 0,1<br />

Port 2<br />

Latch<br />

Port 3<br />

Latch<br />

Figure 1.2. C8051F327 Block Diagram<br />

<strong>C8051F326</strong>/7<br />

Rev. 1.1 15<br />

P<br />

0<br />

D<br />

r<br />

v<br />

P<br />

2<br />

D<br />

r<br />

v<br />

P<br />

3<br />

D<br />

r<br />

v<br />

P0.0/SYSCLK<br />

P0.1<br />

P0.2<br />

P0.3/XTAL2<br />

P0.4/TX<br />

P0.5/RX<br />

P0.6<br />

P0.7<br />

P2.0<br />

P2.1<br />

P2.2<br />

P2.3<br />

P2.4<br />

P2.5<br />

P3.0/C2D

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!