- Page 1 and 2: USB Function Controller - USB speci
- Page 3 and 4: Table of Contents C8051F326/7 1. Sy
- Page 5 and 6: C8051F326/7 12.12.Controlling Endpo
- Page 7 and 8: List of Figures C8051F326/7 1. Syst
- Page 9 and 10: List of Tables C8051F326/7 1. Syste
- Page 11 and 12: List of Registers C8051F326/7 SFR D
- Page 13 and 14: 1. System Overview C8051F326/7 C805
- Page 15 and 16: REGIN VDD GND /RST/C2CK D+ D- VBUS
- Page 17 and 18: 1.1. CIP-51 Microcontroller Core 1.
- Page 19 and 20: 1.2. On-Chip Memory C8051F326/7 The
- Page 21 and 22: 1.5. On-Chip Debug Circuitry C8051F
- Page 23 and 24: 2. Absolute Maximum Ratings Table 2
- Page 25: 4. Pinout and Package Definitions N
- Page 29 and 30: Figure 4.3. QFN-28 Package Drawing
- Page 31 and 32: 5. Voltage Regulator (REG0) C8051F3
- Page 33 and 34: From VBUS From 3 V Power Net VBUS R
- Page 35 and 36: 6. CIP-51 Microcontroller C8051F326
- Page 37 and 38: 6.1.2. MOVX Instruction and Program
- Page 39 and 40: Table 6.1. CIP-51 Instruction Set S
- Page 41 and 42: 6.2. Memory Organization C8051F326/
- Page 43 and 44: 6.2.6. Special Function Registers C
- Page 45 and 46: 6.2.7. Register Descriptions C8051F
- Page 47 and 48: SFR Definition 6.6. B: B Register C
- Page 49 and 50: 6.3.2. External Interrupts C8051F32
- Page 51 and 52: SFR Definition 6.7. IE: Interrupt E
- Page 53 and 54: SFR Definition 6.9. EIE1: Extended
- Page 55 and 56: 6.4. Power Management Modes C8051F3
- Page 57 and 58: 7. Reset Sources C8051F326/7 Reset
- Page 59 and 60: 7.2. Power-Fail Reset / VDD Monitor
- Page 61 and 62: SFR Definition 7.2. RSTSRC: Reset S
- Page 63 and 64: 8. Flash Memory C8051F326/7 On-chip
- Page 65 and 66: 8.2. Non-volatile Data Storage C805
- Page 67 and 68: SFR Definition 8.2. FLKEY: Flash Lo
- Page 69 and 70: 9. External RAM C8051F326/7 The C80
- Page 71 and 72: 10. Oscillators C8051F326/7 C8051F3
- Page 73 and 74: SFR Definition 10.2. OSCICL: Intern
- Page 75 and 76: 10.4. 4x Clock Multiplier C8051F326
- Page 77 and 78:
SFR Definition 10.5. CLKSEL: Clock
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11. Port Input/Output C8051F326/7 O
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11.1. Port I/O Initialization Port
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SFR Definition 11.4. P2: Port2 Bits
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Table 11.1. Port I/O DC Electrical
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12. Universal Serial Bus Controller
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C8051F326/7 USB Register Definition
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C8051F326/7 USB Register Definition
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USB Register Name Table 12.2. USB0
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12.5. FIFO Management C8051F326/7 2
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12.6. Function Addressing C8051F326
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USB Register Definition 12.8. POWER
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12.8. Interrupts C8051F326/7 The re
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C8051F326/7 USB Register Definition
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12.10.2.Endpoint0 IN Transactions C
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C8051F326/7 USB Register Definition
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C8051F326/7 Hardware will automatic
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C8051F326/7 USB Register Definition
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C8051F326/7 USB Register Definition
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Table 12.4. USB Transceiver Electri
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13. UART0 C8051F326/7 UART0 is an a
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BRG Clock = 12 MHz BRG Clock = 24 M
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13.3. Configuration and Operation C
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SFR Definition 13.1. SCON0: UART0 C
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SFR Definition 13.3. SBUF0: UART0 D
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14. Timers C8051F326/7 Each MCU inc
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14.1.2. Mode 1: 16-bit Timer C8051F
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SFR Definition 14.1. TCON: Timer Co
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SFR Definition 14.3. CKCON: Clock C
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15. C2 Interface C8051F326/7 C8051F
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15.2. C2 Pin Sharing C8051F326/7 Th
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NOTES: C8051F326/7 Rev. 1.1 139