C8051F326/7 - Silicon Labs

11. Port Input/Output
C8051F326/7
On-Chip digital resources are available through 15 I/O pins. Port pins are organized as shown in
Figure 11.1. Each of the Port pins can be used as general-purpose I/O (GPIO). Some port pins can be
dedicated to special signals such as /SYSCLK, UART TX and RX, and XTAL2 external clock input.
All Port I/Os are 5 V tolerant (refer to Figure 11.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,2,3). Complete
Electrical Specifications for Port I/O are given in Table 11.1 on page 85.
/SYSCLK
P0.0
P0.1
P0.2
P0.3
P0.4
UART
P0.5
P0.6
P0.7
P2.0
P2.5
P3.0
/INT0
/INT0
XTAL2
C2D
GPIOCN.0
MUX
TMOD.3
TMOD.3
2
6
(P0.0 - OUT)
(P0.0 - IN)
(P0.4 - IN)
(P0.4 - OUT)
(P0.5 - IN)
(P0.5 - OUT)
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cells
I/O
Cells
I/O
Cell
Figure 11.1. Port I/O Functional Block Diagram
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.5
P3.0
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