C8051F326/7 - Silicon Labs

4. Pinout and Package Definitions
Name
Table 4.1. Pin Definitions for the C8051F326/7
Pin Numbers
‘F326 ‘F327
VDD 6 6
VIO
5 —
Type Description
Power
In
Power
Out
Power
In
GND 2 3 Ground.
RST/
C2CK
P3.0/
C2D
REGIN
9 9
10 10
7 7
D I/O
D I/O
D I/O
D I/O
Power
In
VBUS 8 8 D In
D+ 3 4 D I/O USB D+.
D– 4 5 D I/O USB D–.
2.7–3.6 V Core Supply Voltage Input.
C8051F326/7
3.3 V Voltage Regulator Output. See Section 5.
V I/O Supply Voltage Input. The voltage at this pin must be
less than or equal to the Core Supply Voltage (V DD ) for the
'F326. On the 'F327, this pin is internally connected to V DD .
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. See Section 7.
Clock signal for the C2 Debug Interface.
Port 3.0. See Section 11 for a complete description.
Bi-directional data signal for the C2 Debug Interface.
5 V Regulator Input. This pin is the input to the on-chip voltage
regulator.
VBUS Sense Input. This pin should be connected to the
VBUS signal of a USB network. A 5 V signal on this pin indicates
a USB network connection.
P0.0 1 2 D I/O Port 0.0. See Section 11 for a complete description.
P0.1 28 1 D I/O Port 0.1. See Section 11 for a complete description.
P0.2 27 28 D I/O Port 0.2. See Section 11 for a complete description.
P0.3/
XTAL2
26 27
D I/O
D In
Port 0.3. See Section 11 for a complete description.
External Clock Input. See Section 10 for a complete
description.
P0.4 25 26 D I/O Port 0.4. See Section 11 for a complete description.
P0.5 24 25 D I/O Port 0.5. See Section 11 for a complete description.
Rev. 1.1 25