C8051F326/7 - Silicon Labs

10. Oscillators
C8051F326/7
C8051F326/7 devices include a programmable internal oscillator, an external clock input circuit, a low frequency
internal oscillator, and a 4x Clock Multiplier. The internal oscillator can be enabled/disabled and
calibrated using the OSCICN and OSCICL registers, as shown in Figure 10.1. The Low Frequency oscillator
can be enabled/disabled and calibrated using the OSCLCN register, as shown in Figure 10.3. The system
clock (SYSCLK) can be derived from the internal oscillator, external clock, low frequency oscillator, or
the 4x Clock Multiplier divided by 2. The USB clock (USBCLK) can be derived from the internal oscillator
divided by 2, external clock, or 4x Clock Multiplier. Oscillator electrical specifications are given in
Table 10.3 on page 78.
CMOS
Clock
XTAL2
OSCICL OSCICN
Programmable
Internal Clock
Generator
OSCLF
Low Frequency
Oscillator
Input
Circuit
IOSCEN
IFRDY
SUSPEND
EXOSC
MULEN
MULINIT
MULRDY
10.1. Programmable Internal Oscillator
EN
EN
IOSC
IOSC
EXOSC
CLKMUL
Clock Multiplier
Figure 10.1. Oscillator Diagram
All C8051F326/7 devices include a programmable internal oscillator that defaults as the system clock after
a system reset. The internal oscillator period can be adjusted via the OSCICL register. On C8051F326/7
devices, OSCICL is factory calibrated to obtain a 12 MHz frequency. Electrical specifications for the precision
internal oscillator are given in Table 10.3 on page 78. Note that the system clock may be derived from
the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN.
The divide value defaults to 8 following a reset.
IFCN1
IFCN0
n
OSCLEN
MULSEL1
MULSEL0
OSCLCN
x 2 x 2
CLKSEL
USBCLK1
USBCLK0
IOSC / 2
EXOSC
OFF (0 Hz)
CLKSEL2
CLKSL1
CLKSL0
SYSCLK
USBCLK
Rev. 1.1 71
USBCLK1-0