C8051F326/7 - Silicon Labs

C8051F326/7
SFR Definition 11.1. GPIOCN: Global Port I/O Control
R/W R/W R R R R R R/W Reset Value
WEAKPUD INPUTEN — — — — — SYSCLK 01000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xE2
Bit7: WEAKPUD: Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for I/O pins with Port latches set to logic 0 or are configured
to push-pull mode).
1: Weak Pullups disabled.
Bit6: INPUTEN: Global Digital Input Enable.
0: Port I/O input path disabled; Port pins can be used as outputs only.
1: Port I/O input path enabled.
Bits5–1: Unused. Read = 00000b. Write = don’t care.
Bit0: SYSCLK: /SYSCLK Enable
0: /SYSCLK unavailable at P0.0 pin. P0.0 Latch routed to P0.0 pin.
1: /SYSCLK routed to P0.0. P0.0 Latch unavailable at P0.0 pin.
SFR Definition 11.2. P0: Port0
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0x80
Bits7–0: P0.[7:0]
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0).
Read - Always reads ‘0’ if INPUTEN = ‘0’. Otherwise, directly reads Port pin.
0: P0.n pin is logic low.
1: P0.n pin is logic high.
SFR Definition 11.3. P0MDOUT: Port0 Output Mode
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xA4
Bits7–0: Output Configuration Bits for P0.7-P0.0 (respectively):
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
82 Rev. 1.1