PlasmaTherm SLR770 ICP Minispec

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Procedure for gluing silicon wafers together Silicon pieces (< 4 inch) must be glued to a 4 inch silicon carrier wafer in order for the loading mechanism to work. Additionally, if a wafer is to be etched all the way through, the wafer must either have an oxide on the backside or be glued to a 2 nd silicon 4 inch wafer. This is because backside Helium cooling is used on the wafer chuck and once the etch breaks through, the helium leaks into the chamber, raises the pressure and shuts down the machine. Only silicon carrier wafers are used and must be very clean like the sample to be etched. The wafer may be either bare silicon or thermally oxidized silicon. A bare silicon carrier wafer will slow down the etch-rate due to loading effects. For shallow etches, where very fine control is required, this may be desirable. An oxidized carrier wafer will not load down the etch and will result in faster etch rates but less control. This may be desirable for deep etches where speed is required. The following procedure must be used for etching either wafer pieces or all the way through the wafer. It is extremely important that no air bubbles be trapped in the PR as this will cause the piece to flip over during pumpdown or etch. You should firmly rub the piece onto the 4 inch wafer to remove air and/or use the vacuum bake oven. Additionally grooves on the underside of your piece will aid in allowing air to escape. PIECES: 1 Use a Q-tip swab to dab a small drop of AZ5214 resist (or equivalent) on the backside of your piece. 2 Then carefully center the backside of your piece onto the front-side of the carrier wafer and press down firmly. Do NOT use too much resist as this will be squeezed out from the back when you press down and can cause problems. 3 Bake your sample on a hot plate at 120°C for at least 3 minutes. This hardens the resist. Do not allow the backside of the carrier wafer to become contaminated (eg from the hot plate). 4 Let your sample cool and bring it to the DRIE machine and follow the loading procedures as outlined in the SLR 770 <strong>ICP</strong> spec. WHOLE WAFERS 1 Use a Q-Tip swab as above but put 2 or 3 small drops on the backside of your 4 inch wafer near the center spaced about 1/2 inch apart. 2 Carefully center the backside of your wafer over the carrier wafer and press down firmly. Make sure the flats for both wafers line up before pressing the substrates together. 3 Bake your sample on a hot plate at 120°C for at least 3 minutes. This hardens the resist. Do not allow the backside of the carrier wafer to become contaminated (eg from the hot plate). 4 Let your sample cool and bring it to the DRIE machine and follow the loading procedures as outlined in the SLR 770 <strong>ICP</strong> spec.
Additional Information on DRIE 1 For resist thicknesses < 2-3 µm, edge bead removal is probably not necessary if the resist is baked. Thicker films > 8µm, can outgas and cause clamping problems. Removal of the edge bead is advised in these cases. 2 Resist profile will affect the etch and sidewall profile. When baking resist, avoid too high a temperature such that the resist flows (unless you are trying to get a taper). 3 Small silicon pieces can be “glued” to a 4 inch silicon wafer using a dab of PR. If an oxidized wafer is used, the etch rate will be very fast which may lead to control problems. A bare silicon wafer will slow the etch down for better control. In any event, you must use a 4 inch wafer as a carrier. 4 Silicon etch rate is a strong function of exposed silicon (usually expressed as % open Si). Etching slows down dramatically as the amount of exposed area goes up, so keeping track of exposed area is important. 5 Some standard Bosch specs for 10-15% exposed area are: * 1-3 µm/ minute silicon etch rate * Large open areas etch faster than smaller * Uniformity of etch and other parameters within 5% across 4 inch wafer * 75-80:1 selectivity to PR for 12% open Si and 2-100 µm lines * ~150:1 selectivity to thermal oxide (12% open Si area); PECVD oxide not as good. * Sidewall angle depends on aspect ratio (Depth to width of trench) and is 88-92 Deg. If process is tuned for 90 Deg at 20 µm, then larger openings will be reentrant (neg Slope). Conversely if the process is tuned for 90 Deg at larger openings, a positive taper will result at smaller openings. 6 Run to run uniformity should be about 2 %. 7 For open areas >20%, a bulls-eye pattern can be seen with outer edges etching faster than the center due to mass loading/gas depletion effects. 8 A seasoning run should be made after opening the process chamber or doing any substantial maintenance. This involves running the standard Bosch process on a dummy silicon or oxide wafer (to protect cathode). Depending on total etch time, some haze may be seen at wafer edges and is considered normal. 9 A cleaning run is not normally needed unless the process chamber is opened and the fixturing is changed. If so the recipe is: * 80 sccm O2 + 20 sccm Ar @12 mT
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PlasmaTherm SLR770 ICP Minispec

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