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BBC Microcomputer Service Manual Oct 1985 Section 1 BBC Micro ...

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In the other screen modes, the information is stored in RAM as actual<br />

bit patterns for every character that is written to the screen. This is<br />

expensive in terms of memory usage, (between 8K and 20K in the<br />

different modes) but it makes it extremely versatile, especially when<br />

mixing graphics with text. The addressing of the RAM for the different<br />

modes is performed by the 6845 CRT controller, whilst the data is taken<br />

from the RAM and serialised by a custom designed circuit, known as the<br />

video processor. This data is not used directly to produce RGB<br />

information, but can be thought of as a set of logical colour numbers<br />

which are passed to an area of high speed RAM within the video<br />

processor referred to as the colour palette. This determines, for each<br />

logical colour number, which combination of red, green and blue is<br />

produced, and whether or not the colour is flashing. The video<br />

processor is also responsible for selecting either the RGB signals<br />

coming from the Teletext chip or the signals coming from the palette<br />

and sending them out to the RGB buffers and the PAL encoder.<br />

This RGB information is presented, after buffering, on the RGB<br />

connector. To provide a UHF output, the RGB signals are combined with<br />

the sync signals and fed into a UHF modulator. A video output is also<br />

provided which consists of a summing of the RGB signals in such a way<br />

as to give an appropriate grey scale. On issue 4 boards onwards, the<br />

option is given of adding colour to the video signal in order to<br />

provide a PAL encoded video output. [See section 3.4]<br />

Moving on round in an anti-clockwise direction we come to the two<br />

serial interfaces, the cassette interface and the RS423. These<br />

facilities are both provided by a standard ACIA (Asynchronous<br />

Communications Interface Adaptor) - the 6850, and a custom designed<br />

circuit referred to as, the serial processor. This processor contains<br />

the programmable baud rate generators for transmit and receive which<br />

provide the clocks for the ACIA. The ACIA itself is responsible for<br />

serialising the data, providing the control lines for the RS423 and<br />

generating interrupts, whilst the serial processor switches these data<br />

and control lines between the cassette and RS423 interfaces. The serial<br />

processor also provides data separator and sinewave synthesis circuits<br />

for the cassette recorder as well as a means of detecting the presence<br />

of the incoming tone from the recorder. [See section 3.5]<br />

The next section is the analogue input port which is a four channel 12<br />

bit converter which is discussed in more detail in section 3.9 and the<br />

interfacing survey (see chapter 7).<br />

In the NW corner is the Econet section which centres around a 68B54<br />

Advanced Data-Link Controller (ADLC). This is a sophisticated serial<br />

communications device allowing the sending and receiving of data at a<br />

variety of speeds between as many as 254 computers. The data transfer<br />

is synchronised by a clock signal fed to all the computers as a<br />

differential signal on one pair of cables, whilst the data itself uses<br />

another pair of cables. Data is both transmitted and received on the<br />

same pair of cables, but obviously only one computer at a time is able<br />

to "broadcast" onto the data highway. [See section 3.12]<br />

7

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