BBC Microcomputer Service Manual Oct 1985 Section 1 BBC Micro ...

A 555 timer circuit (IC16) provides a reset signal both at power up and
also when the BREAK key is pressed. There is also a separate reset
circuit using a CR combination from the +5 volt power supply (C10 and
R20 and D1), to provide a signal called Reset A which is fed to IC3,
the internal VIA. The idea is that although the 555 timer produces a
general reset at power up or when the BREAK key is pressed, Reset A
goes low only on power up. By interrogating the interrupt register on
IC3 on the occurrence of a general reset, the microprocessor can
discover Whether it was a "cold start", ie power up, or a "warm start",
ie the BREAK key has been pressed when the system has already been in
use for some time.
3.2 Memory and address decoding
31 1/4 Kbytes of ROM are catered for in the address map. 15 1/4 Kbytes
of this ae contained in the operating system (IC51). This is in fact a
16K device but 3/4K of it is left unused and it is in this area that
the I-0 device memory map is situated. Four other ROMs (ICs 52, 88,
100 and 101) are on the main circuit board. They may all be 16 Kbyte
devices, in which case any one of them may be switched into the 16
Kbyte space in the memory map by writing to the ROM select latch (IC76)
. Alternatively, four 4 Kbyte ROMs may be in these four sockets in
order to fill the 16 Kbyte space assigned. In this case, a two line to
four line decoder (half of IC20) is used to select which of the four
devices is being addressed by the address lines Al2 and A13. Mixtures
of these two cases are allowed for, for instance two pairs of 8 Kbyte
ROMs, one pair or the other being selected by the ROM select latch and
then the ROM to be used in each pair being selected by the 2-4 line
address decoder. Address decoding for the ROMs is by IC21 which decodes
memory addresses &8000 to &C000 and &C000 to &FFFF. Locations from 0 -
&7FFF are assigned to the dynamic RAM, and this is decoded by feeding
A15 into pin 4 of IC21. All the rest of the hardware is mapped within
locations &FC00 to &FEFF. This is decoded by IC22, whilst ICs 20 and 25
are used to mask off the ROM over this range of addresses. ICs 24 and
26 decode the individual devices within this range, some of which are
read or write only. IC23 detects when a slow 1 MHz device is being
addressed and it calls for the 6502 to execute a slow clock cycle.
Note that in early versions of the BBC Microcomputer, the operating
system was contained within 4 EPROMs in IC positions 52, 88, 100 and
101 while the BASIC interpreter was located in IC51. This arrangement
is abnormal and has been phased out. Refer to the link selection survey
(5.1) for more detailed information on this.
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