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General Computer Science 320201 GenCS I & II Lecture ... - Kwarc

General Computer Science 320201 GenCS I & II Lecture ... - Kwarc

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The capacity of RAM chips doubles approximately every year.<br />

c○: Michael Kohlhase 271<br />

One aspect of this is particularly interesting – and user-visible in the sense that the division of<br />

storage addresses is divided into a high- and low part of the address. So we we will briefly discuss<br />

it here.<br />

Layout of Memory Chips<br />

To take advantage of the two-dimensional nature of the chip, storage elements are arranged<br />

on a square grid. (columns and rows of storage elements)<br />

For example, a 1 Megabit RAM chip has of 1024 rows and 1024 columns.<br />

identify storage element by its row and column “coordinates”. (AND them for addressing)<br />

Hence, to select a particular storage<br />

location the address information must<br />

be translated into row and column<br />

specification.<br />

The address information is divided<br />

into two halves; the top half is used<br />

to select the row and the bottom half<br />

is used to select the column.<br />

c○: Michael Kohlhase 272<br />

151

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