24-Bit, 192-kHz Sampling, Advanced Segment, Audio Stereo DAC ...

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Write Register
SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006
A master can write to any PCM1792A registers using single or multiple accesses. The master sends a PCM1792A slave
address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting
register, followed by the data to be transferred. When the data are received properly, the index register is incremented by
1 automatically. When the index register reaches 0x7F, the next value is 0x0. When undefined registers are accessed, the
PCM1792A does not send an acknowledgement. Figure 33 is a diagram of the write operation.
Transmitter M M M S M S M
Data Type St Slave Address W ACK Reg Address ACK Write Data 1
Read Register
M: Master Device S: Slave Device
St: Start Condition ACK: Acknowledge Sp: Stop Condition W: Write
Figure 33. Write Operation
S
ACK
M
Write Data 2
A master can read the PCM1792A register. The value of the register address is stored in an indirect index register in
advance. The master sends a PCM1792A slave address with a read bit after storing the register address. Then the
PCM1792A transfers the data which the index register points to. When the data are transferred during a multiple access,
the index register is incremented by 1 automatically. (When first going into read mode immediately following a write, the
index register is not incremented. The master can read the register that was previously written.) When the index register
reaches 0x7F, the next value is 0x0. The PCM1792A outputs some data when the index register is 0x10 to 0x1F, even if
it is not defined in Table 4. Figure 34 is a diagram of the read operation.
Transmitter M M M S M S M M
Data Type St Slave Address W ACK Reg Address ACK Sr Slave Address
S
ACK
Data
S
ACK
Slave M
M: Master Device S: Slave Device
St: Start Condition Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge
W: Write R: Read
Noise Suppression
Figure 34. Read Operation
The PCM1792A incorporates noise suppression using the system clock (SCK). However, there must be no more than two
noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz in fast mode.
However, it works incorrectly in the following conditions.
Case 1:
1. t (SCK) > 120 ns (t (SCK): period of SCK)
2. t (HI) + t (D−HD) < t (SCK) × 5
3. Spike noise exists on the first half of the SCL HIGH pulse.
4. Spike noise exists on the SDA HIGH pulse just before SDA goes LOW.
SCL
SDA
Noise
When these conditions occur at the same time, the data is recognized as LOW.
M
R
ACK
S
ACK
S
NACK
M
Sp
M
Sp
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