24-Bit, 192-kHz Sampling, Advanced Segment, Audio Stereo DAC ...

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TIMING DIAGRAM
SDA
SCL
t(BUF)
t(S-HD)
Start
t(D-SU)
t(LOW)
t(SCL-F)
t(SCL-R)
t(HI)
t(D-HD)
Repeated Start
t(RS-SU)
SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006
t(RS-HD)
t(SDA-R)
t(SP)
t(SDA-F)
t(P-SU)
TIMING CHARACTERISTICS
PARAMETER CONDITIONS MIN MAX UNIT
f(SCL) f(SCL)
t(BUF) t(BUF)
t(LOW) t(LOW)
t(HI) t(HI)
SCL clock frequency
Bus free time between stop and start conditions
Low period of the SCL clock
High period of the SCL clock
t(RS-SU) t(RS-SU) Setup time for (repeated) start condition
t(S-HD)
t(RS-HD)
t(D-SU) t(D-SU)
t(D-HD) t(D-HD)
Hold time for (repeated) start condition
Data setup time
Data hold time
t(SCL-R) t(SCL-R) Rise time of SCL signal
Standard 100
Fast 400
Standard 4.7
Fast 1.3
Standard 4.7
Fast 1.3
Stop
kHz
µs
µs
Standard 4 µs
Fast 600 ns
Standard 4.7 µs
Fast 600 ns
Standard 4 µs
Fast 600 ns
Standard 250
Fast 100
Standard 0 900
Fast 0 900
Standard 20 + 0.1 CB 1000
Fast 20 + 0.1 CB 300
t(SCL-R1) Rise time of SCL signal after a repeated start condition and after an Rise time of SCL signal after a repeated start condition and after an
Standard 20 + 0.1 CB 1000
t(SCL-R1)
acknowledge bit Fast 20 + 0.1 CB 300
t(SCL-F) t(SCL-F) Fall time of SCL signal
t(SDA-R) t(SDA-R) Rise time of SDA signal
t(SDA-F) t(SDA-F) Fall time of SDA signal
t(P-SU) t(P-SU)
Setup time for stop condition
Standard 20 + 0.1 CB 1000
Fast 20 + 0.1 CB 300
Standard 20 + 0.1 CB 1000
Fast 20 + 0.1 CB 300
Standard 20 + 0.1 CB 1000
Fast 20 + 0.1 CB 300
ns
ns
ns
ns
ns
ns
ns
Standard 4 µs
Fast 600 ns
C(B) Capacitive load for SDA and SCL lines 400 pF
t(SP) Pulse duration of suppressed spike Fast 50 ns
VNH VNH
Noise margin at high level for each connected device (including hysteresis)
Standard
Fast 0.2 VDD V
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