Requirements for Unity of Application - Japan Patent Office

[Example 11]
[Title of the Invention]
Multiplex transmission circuit and receiver circuit
[Claims]
1. A multiplex transmission circuit comprising an input register (304) storing a primary data
character of start-stop system to be transmitted, an inputting process of a secondary data
character (302) receiving the secondary data character such as status control signals, an
output registers (305), a gate (330-332) transferring primary data characters to the output
register (305) from the input register (304) when the output register is open and the input
register is full, a transfer device (351) transferring a secondary character with given
instruction bit to the output register (305) from the secondary data input system when the
input register (304) is not full, a means to output data character in the output register to
output line (110). (See Figure 1)
2. A distributing receiving circuit having input register (410) for storing the primary and
secondary data characters received, an output registers (425) storing a primary data
character and secondary data register (430) storing a secondary data character, and
distributing data characters to an output register and secondary data register according to
mark instruction bit. (See Figure 2)
[Excerpt from Detailed Description of the Invention and Drawings]
In data communication of computers, transmission of various secondary data such as
supervisor, status control signals and channel confirmation signals is required. In the prior art,
one of the channels is assigned specifically for transmission of secondary data when it is
transmitted on time sharing multiplex.
This invention related to a multiplex transmission circuit in time sharing transmission in
which control data are automatically inserted when the time slot assigned to each channel is
open and setting the channel specified for the secondary data is not needed. This also
concerns a distributing reception circuit, which is used for separating the secondary data from
the signals transmitted by sharing time.
Figure 1 Multiplex transmission circuit
34