Requirements for Unity of Application - Japan Patent Office
Requirements for Unity of Application - Japan Patent Office
Requirements for Unity of Application - Japan Patent Office
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[Example 40]<br />
[Title <strong>of</strong> the Invention]<br />
MIS type semiconductor device and the semiconductor random access memory device<br />
application<br />
[Claims]<br />
1. MIS type semiconductor device, comprising first MIS element (Q W11 ) <strong>for</strong>med on the<br />
semiconductor substrate, utilizing either the drain (3) or the source (4) <strong>of</strong> the first MIS<br />
element (Q W11 ) and the second MIS element (Q R11 ) <strong>for</strong>med above the first MIS element<br />
(Q W11 ). (See Figure 1)<br />
2. A semiconductor random access memory device with the characteristics <strong>of</strong> having the<br />
matrix <strong>of</strong> memory cells (C11) that includes the first MIS element (Q W11 ), the drain (3) or the<br />
source (4) <strong>of</strong> the first MIS element (Q W11 ) and the second MIS element (Q R11 ) <strong>for</strong>med<br />
above the first MIS element (Q W11 ), gate input capacity in<strong>for</strong>mation storage capacitor<br />
(C S11 ) <strong>for</strong> the second MIS element (Q W11 ). In the matrix <strong>of</strong> the memory array, the drain <strong>of</strong><br />
the said first MIS element (Q W11 ) electrically connected to the drain <strong>of</strong> the second MIS<br />
element (Q W11 ), … connecting so that the data line (D 1 ) orthogonally to sense (S 1 ) and<br />
word (W 1 ) lines <strong>of</strong> the each memory cell <strong>of</strong> the array. (See Figure 2)<br />
[Excerpt from Detail Description <strong>of</strong> the Invention and Drawings]<br />
This invention concerns the MIS semiconductor device and a high-integrated random<br />
access memory semiconductor device. This memory cell is composed <strong>of</strong> two MIS elements<br />
<strong>for</strong>ming specific circuit in the memory cell circuit and a capacitor in which the first MIS element<br />
(Q W11 ) and the second MIS element (Q R11 ) <strong>for</strong>med above the <strong>for</strong>mer, further the either the<br />
source or drain <strong>of</strong> the first MIS element (Q W11 ) is made function as the gate to the second MIS<br />
element (Q R11 ) carrying a capacitor (C S11 ) thereby achieving a semiconductor random access<br />
memory device which is simplified.<br />
Figure 1 Figure 2<br />
[Explanation]<br />
The technical fields <strong>of</strong> the specified invention (Claim 1) and related invention (Claim 2) are<br />
"MIS type semiconductor device" and "semiconductor random access memory device<br />
application". <strong>Application</strong> <strong>of</strong> the art <strong>of</strong> the technical field <strong>of</strong> MIS type semiconductor device to the<br />
technical field <strong>of</strong> semiconductor random access memory consisting <strong>of</strong> many circuit elements is<br />
extremely appropriate. The technical fields <strong>of</strong> both inventions are related directly and<br />
technically, there<strong>for</strong>e their industrial fields <strong>of</strong> application <strong>of</strong> both inventions are the same.<br />
The semiconductor device that is the new matter corresponding to the problem to be solved<br />
<strong>of</strong> the specified invention is substantial part <strong>of</strong> matters in the claim <strong>of</strong> the related invention.<br />
There<strong>for</strong>e the substantial parts <strong>of</strong> matters in the claims <strong>of</strong> the inventions are the same.<br />
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