User's Manual 686LCD/S & 686LCD/MG CPU Board

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686LCD/S & 686LCD/MG CPU Board - Version 1.4.0 - 8. December 1997 5.3 I/O - Map. The board incorporates a fully ISA Bus Compatible master and slave interface. The drive capabilities allow for up to five external ISA slots to be driven without external data buffers. The accessable I/O area on the ISA-bus is 64Kbytes with 16 address bits, whereas the accessable Memory area is 16Mbytes with 24 address bits. Certain I/O addresses are subject to change during boot as PnP managers may relocate devices or functions. The addresses shown in the table are typical locations I/O Port Access Read/ Description Write 0000h - 001Fh are used by the 8237 Compatible DMA Controller 1 DMA Current Address and Byte Count Registers 0000h PCI R/W DMA channel 0 Address bits [15:0] : byte 0 (low byte), followed by byte 1. 0001h PCI R/W DMA channel 0 Byte count [15:0] : byte]0 (low byte), followed by byte 1. 0002h PCI R/W DMA channel 1 Address bits [15:0] : byte 0 (low byte), followed by byte 1. 0003h PCI R/W DMA channel 0 Byte count [15:0] : byte]0 (low byte), followed by byte 1. 0004h PCI R/W DMA channel 2 Address bits [15:0] : byte 0 (low byte), followed by byte 1. 0005h PCI R/W DMA channel 2 Byte count [15:0] : byte]0 (low byte), followed by byte 1. 0006h PCI R/W DMA channel 3 Address bits [15:0] : byte 0 (low byte), followed by byte 1. 0007h PCI R/W DMA channel 3 Byte count [15:0] : byte]0 (low byte), followed by byte 1. DMA Status and Command Register Ch.0-3 0008h PCI R DMA channels 0-3 status register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 Channel 3 request Channel 2 request Channel 1 request Channel 0 request Terminal count on channel 3 Terminal count on channel 2 Terminal count on channel 1 Terminal count on channel 0 0008h PCI W DMA channels 0-3 command register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - DACK sense active low DACK sense active high DREQ sense active low DREQ sense active high Late write selection Extended write selection Fixed priority Rotating priority Normal timing Compressed timing Enable controller Disable controller Disable memory-to-memory transfer Enable memory-to-memory transfer Reserved DMA Request Register 0009h PCI W DMA write request register Bits 7-3 0 Reserved. Must be 0. Bit 2 0 Resets individual DMA Channel Service SW Request 1 Sets the request bit. Bit 1-0 00 DMA Channel 0 select 01 DMA Channel 1 select 10 DMA Channel 2 select 11 DMA Channel 3 select INSIDE Technology A/S. Page 32 of 134
I/O Port Access Read/ Write DMA Mask Register 686LCD/S & 686LCD/MG CPU Board - Version 1.4.0 - 8. December 1997 000Ah PCI W DMA channel 0-3 mask register Bits 7-3 Bit 2 Bit 1-0 DMA Channel Mode Register 000Bh PCI W DMA channel 0-3 write mode register Bits 7-6 00 01 10 11 Bit 5 0 1 Bit 4 0 1 Bit 3-2 Bits 1-0 - 0 1 00 01 10 11 00 01 10 11 00 01 10 11 Description Reserved. Must be 0. Enable DREQ for the selected channel. Disable DREQ for the selected channel. Channel select Channel 0 Channel 1 Channel 2 Channel 3 Transfer Mode select Demand mode Single mode Block mode Cascade mode Address increment Address decrement Disable auto-initialization Enable auto-initialization Select type of operation Verify operation Write to memory Read from memory Reserved Channel select Channel 0 Channel 1 Channel 2 Channel 3 Misc. DMA Registers 000Ch PCI W DMA 1 Clear byte pointer flip/flop. Command enabled with a write to the I/O port address. 000Dh PCI W DMA 1 Master Clear Register. Same effect as HW reset. Command enabled with a write to the I/O port address. 000Eh PCI W DMA 1 Clear Mask Register. Enables acceptance of DMA requests for all four channels. Command enabled with a write to the I/O port address. 000Fh PCI R/W DMA 1 Mask Register, read/write all mask bits. Bits 7-4 0 Reserved. Must be 0. Channel Mask Bits Bit 3 0 Disable ch. 3 DREQ 1 Enable ch. 3 DREQ Bit 2 0 Disable ch. 2 DREQ 1 Enable ch. 2 DREQ Bit 1 0 Disable ch. 1 DREQ 1 Enable ch. 1 DREQ Bit 0 0 Disable ch. 0 DREQ 1 Enable ch. 0 DREQ 0020h – 0021h are used by the 8259 compatible Programmable interrupt controller 1 Int. 1 Control 0020h PCI/ISA W Initialization Command Word 1 Register. Set Bit 4 to 1 to access ICW1. Bit 7-5 Bit 4 Bit 3 Bit 2 000 0 1 0 - ICW/OCW select. These bits should be 000 when programming the PIIX Must be 0 during writes to OCW2 and OCW3. Select ICW1 Edge Level Bank Select. This bit is disabled. Its function is replaced by the Edge/Level Triggered Control Registers. ADI. Ignored for PIIX. Bit 1 Bit 0 0 1 Single or Cascade. Must be 0. ICW4 Write Required. Must be set to 1. INSIDE Technology A/S. Page 33 of 134
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User's Manual 686LCD/S & 686LCD/MG CPU Board

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