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Qualcomm's Assessment of 3D Interconnect Equipment ... - Sematech

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300mm <strong>Equipment</strong>/Process/Materials Gaps Table<br />

High – Level Module<br />

<strong>Equipment</strong><br />

Process<br />

Material<br />

Wafer crack during demount<br />

Adhesive max temperature<br />

Carrier (Mount/Demount)<br />

Lead time, cost<br />

µbump<br />

conformality<br />

Carrier material selection<br />

Number <strong>of</strong> carrier cycles<br />

Adhesive residue<br />

TSV Contact preparation<br />

CMP<br />

PECVD<br />

TTV process optimization<br />

Passivation material<br />

(stress/temperature)<br />

RDL<br />

BF Alignment<br />

Stepper resolution<br />

Planarity<br />

Polymer temperature<br />

T2T Bonding<br />

Bonding accuracy<br />

Under fill<br />

Material stack up<br />

TSS stack assembly<br />

TSS stack bumping<br />

Thomas R Toms July 16, 2008<br />

PAGE 23<br />

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