Qualcomm's Assessment of 3D Interconnect Equipment ... - Sematech

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A TSS case study What impact does the TSV type, TSV pitch, # of tiers, TSV farm size, TSV size, bonding order, Metallization layers and T2T bonding pitch have on the COO and Yield Factors TSV 1 st or Last Power delivery (PDN) A single supply, Number of TSS tiers, intra-tier I*R losses and TSV I*R losses External I/O count and Si tier size For this study the I/O count was fixed at 400 The number of T2T signals (non-power/ground) Via last - 200 (the approximate I/O count for two 64 bit channels of DDR1 memory) Via 1 st - 2500 (arbitrarily selected) The Si tier size Base tier size of 50 – 100mm 2 Thomas R Toms July 16, 2008 PAGE 8
TSV selection TSV Keep Out Area (KOA) and availability Via Last Via 1 st 6000 150 KOA ( (µm 2 /TSV) 5000 4000 3000 2000 1000 125 100 75 50 25 0 Today 2009 2010 0 Today 2010 200mm Wafers 300mm Wafers 200mm Wafers 300mm Wafers (50um) 300mm Wafers (25um) Thomas R Toms July 16, 2008 PAGE 9
Page 1 and 2: An Assessment of 3D Interconnect, E
Page 3 and 4: Outline • Terminology • Growth
Page 5 and 6: Growth in mobile and wireless marke
Page 7: ITRS Draft Specification for 3D 30K
Page 11 and 12: Power & Ground in a TSS stack How m
Page 13 and 14: Factors that impact Tier thickness
Page 15 and 16: Feature size vs. Throughput and Yie
Page 17 and 18: Concluding remarks To improve the s
Page 19 and 20: Thank You PAGE 19
Page 21 and 22: Calculation of TSV count for 1% tie
Page 23: 300mm Equipment/Process/Materials G

Qualcomm's Assessment of 3D Interconnect Equipment ... - Sematech

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