CoreSight SoC Technical Reference Manual - ARM Information Center

More documents

Recommendations

Info

Chapter 1 Introduction This chapter introduces CoreSight SoC. It contains the following sections: • About CoreSight SoC on page 1-2. • CoreSight SoC block summary on page 1-4. • Typical CoreSight debugging environment on page 1-6. • Product revisions on page 1-7. ARM DDI 0480D Copyright © 2011, 2012 ARM. All rights reserved. 1-1 ID010213 Non-Confidential
Introduction 1.1 About CoreSight SoC CoreSight SoC is a set of highly configurable components that you can use to: • Graphically configure all acceptable configuration options of components using AMBA Designer. • Build systems that integrate CoreSight SoC components and processors. Note You can also integrate other CoreSight components like System Trace Macrocell (STM) and Trace Memory Controller (TMC) that are licensed separately. • Run the design rule checks to ensure that the configurations match the compliance limitations. • Create a testbench infrastructure to run system-level tests to verify the debug and trace system operation. 1.1.1 CoreSight SoC features CoreSight SoC has the following features: • Configurability. • Debug and trace visibility of whole systems. • Cross triggering support between System-on-Chip (SoC) subsystems. • Multi-source trace in a single stream. • Higher data compression than previous solutions. • Standard programmers models for tool support. • Open interfaces for third-party IP. • Low pin count. • Low silicon overhead. 1.1.2 Structure of CoreSight SoC The CoreSight SoC components are grouped into the following categories: Control and access components Provide access to other debug components and control of debug behavior. Examples include: • DAP. See Chapter 4 Debug Access Port. • The Embedded Cross Trigger (ECT). See Chapter 4 Debug Access Port. Sources Links Generate trace data for output through the Advanced Trace Bus (ATB). Examples include: • Program Trace Macrocell (PTM). • System Trace Macrocell (STM), documented separately. See Additional reading on page ix. • CoreSight Embedded Trace Macrocells (ETMs), documented separately. See Additional reading on page ix. Provide connection, triggering, and flow of trace data. Examples include: • Synchronous 1:1 ATB bridge. ARM DDI 0480D Copyright © 2011, 2012 ARM. All rights reserved. 1-2 ID010213 Non-Confidential
Page 1 and 2: CoreSight SoC Revision: r2p1 Techni
Page 3 and 4: Contents CoreSight SoC Technical Re
Page 5 and 6: 8.11 Example configuration scenario
Page 7 and 8: Preface About this book This is the
Page 9 and 10: Preface Clock HIGH to LOW Transient
Page 11: Preface Feedback ARM welcomes feedb
Page 15 and 16: Introduction 1.2 CoreSight SoC bloc
Page 17 and 18: Introduction 1.3 Typical CoreSight
Page 19 and 20: Chapter 2 Functional Overview This
Page 21 and 22: Functional Overview The SoC designe
Page 23 and 24: Functional Overview Clock and reset
Page 25 and 26: Functional Overview The following c
Page 27 and 28: Functional Overview 2.2 Advanced Tr
Page 29 and 30: Functional Overview Note In Figure
Page 33 and 34: Functional Overview The timestamp e
Page 41 and 42: Functional Overview 2.6.3 Event asy
Page 43 and 44: Chapter 3 Programmers Model This ch
Page 45 and 46: Programmers Model 3.2 Granular Powe
Page 47 and 48: Programmers Model 31 30 29 28 27 26
Page 49 and 50: Programmers Model Table 3-2 CPWRUPR
Page 51 and 52: Programmers Model 31 30 29 28 27 26
Page 53 and 54: Programmers Model Table 3-3 CPWRUPA
Page 55 and 56: Programmers Model Table 3-4 shows t
Page 57 and 58: Programmers Model 3.3.7 Lock Status
Page 59 and 60: Programmers Model Table 3-10 shows
Page 61 and 62: Programmers Model Table 3-13 shows
Page 63 and 64:
Programmers Model 3.3.16 Peripheral
Page 65 and 66:
Programmers Model 3.3.19 Component
Page 67 and 68:
Programmers Model 3.4 APB interconn
Page 69 and 70:
Programmers Model Table 3-24 ROM_EN
Page 71 and 72:
Page 73 and 74:
Programmers Model 3.5.8 Component I
Page 75 and 76:
Programmers Model Figure 3-32 shows
Page 77 and 78:
Programmers Model 3.7 ATB funnel re
Page 79 and 80:
Programmers Model Table 3-36 Ctrl_R
Page 81 and 82:
Programmers Model Table 3-37 Priori
Page 83 and 84:
Programmers Model Attributes See th
Page 85 and 86:
Programmers Model Table 3-38 ITATBD
Page 87 and 88:
Programmers Model 3.7.6 Integration
Page 89 and 90:
Programmers Model Table 3-43 shows
Page 91 and 92:
Page 93 and 94:
Programmers Model 3.7.14 Device Typ
Page 95 and 96:
Programmers Model 31 8 7 0 Reserved
Page 97 and 98:
Programmers Model 31 8 7 4 3 0 Rese
Page 99 and 100:
Page 101 and 102:
Programmers Model 3.9 ATB replicato
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
Programmers Model 3.9.7 Claim Tag C
Page 109 and 110:
Programmers Model 3.9.10 Authentica
Page 111 and 112:
Page 113 and 114:
Page 115 and 116:
Programmers Model Usage constraints
Page 117 and 118:
Page 119 and 120:
Programmers Model Table 3-83 ETB re
Page 121 and 122:
Page 123 and 124:
Programmers Model to determine the
Page 125 and 126:
Programmers Model 3.11.8 ETB RAM Wr
Page 127 and 128:
Programmers Model 31 14 13 12 11 10
Page 129 and 130:
Programmers Model 3.11.12 Integrati
Page 131 and 132:
Programmers Model Table 3-97 ITATBD
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Programmers Model 31 8 7 6 5 4 3 2
Page 139 and 140:
Programmers Model 3.11.26 Periphera
Page 141 and 142:
Page 143 and 144:
Page 145 and 146:
Page 147 and 148:
Programmers Model Offset Name Type
Page 149 and 150:
Page 151 and 152:
Programmers Model Bits Name Functio
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Programmers Model 3.13.14 CTI Chann
Page 159 and 160:
Programmers Model 3.13.17 CTI Chann
Page 161 and 162:
Page 163 and 164:
Programmers Model Bits Name Functio
Page 165 and 166:
Programmers Model 3.13.26 Enable CT
Page 167 and 168:
Programmers Model Figure 3-142 show
Page 169 and 170:
Programmers Model Attributes See th
Page 171 and 172:
Page 173 and 174:
Programmers Model 3.13.40 Lock Stat
Page 175 and 176:
Page 177 and 178:
Page 179 and 180:
Programmers Model Table 3-167 PIDR2
Page 181 and 182:
Page 183 and 184:
Programmers Model 3.14 TPIU registe
Page 185 and 186:
Programmers Model 3.15 TPIU registe
Page 187 and 188:
Programmers Model Table 3-174 Suppo
Page 189 and 190:
Programmers Model Table 3-174 Suppo
Page 191 and 192:
Programmers Model Table 3-175 Curre
Page 193 and 194:
Programmers Model Table 3-175 Curre
Page 195 and 196:
Programmers Model Configurations Th
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Programmers Model Note ARM recommen
Page 203 and 204:
Programmers Model inserted during n
Page 205 and 206:
Page 207 and 208:
Programmers Model Table 3-189 ITATB
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
Programmers Model 31 8 7 6 5 4 3 2
Page 215 and 216:
Page 217 and 218:
Programmers Model 3.15.31 Periphera
Page 219 and 220:
Page 221 and 222:
Page 223 and 224:
Programmers Model Table 3-212 AHB-A
Page 225 and 226:
Programmers Model Table 3-216 JTAG-
Page 227 and 228:
Programmers Model Table 3-217 JTAG-
Page 229 and 230:
Programmers Model 3.17.2 AHB-AP reg
Page 231 and 232:
Programmers Model AHB-AP Data Read/
Page 233 and 234:
Programmers Model 31 30 28 27 24 23
Page 235 and 236:
Programmers Model AXI-AP Data RW Re
Page 237 and 238:
Programmers Model AXI-AP Debug Base
Page 239 and 240:
Programmers Model • APB-AP Banked
Page 241 and 242:
Programmers Model APB-AP Data Read/
Page 243 and 244:
Programmers Model Accesses to this
Page 245 and 246:
Programmers Model the APnDP bit = 0
Page 247 and 248:
Programmers Model 31 24 23 8 7 4 3
Page 249 and 250:
Programmers Model SW-DP only 31 10
Page 251 and 252:
Programmers Model • Accessed by a
Page 253 and 254:
Programmers Model Table 3-251 Times
Page 255 and 256:
Programmers Model 31 1 0 RESERVED R
Page 257 and 258:
Page 259 and 260:
Page 261 and 262:
Page 263 and 264:
Debug Access Port 4.1 About the Deb
Page 265 and 266:
Debug Access Port APB-Multiplexer A
Page 267 and 268:
Debug Access Port DAP internal bus
Page 269 and 270:
Debug Access Port to continually re
Page 271 and 272:
Debug Access Port The SW-DP clock,
Page 273 and 274:
Debug Access Port Figure 4-7 shows
Page 275 and 276:
Debug Access Port Table 4-4 TARGETI
Page 277 and 278:
Debug Access Port 4.3 DAPBUS interc
Page 279 and 280:
Debug Access Port 4.5 DAP synchrono
Page 281 and 282:
Debug Access Port In this way, the
Page 283 and 284:
Debug Access Port 4.8 JTAG-AP The J
Page 285 and 286:
Debug Access Port 4.9 AXI-AP The AX
Page 287 and 288:
Debug Access Port Similarly, after
Page 289 and 290:
Debug Access Port Unaligned accesse
Page 291 and 292:
Debug Access Port 4.10 AHB-AP The A
Page 293 and 294:
Debug Access Port • Packed transf
Page 295 and 296:
Debug Access Port 4.11 APB-AP The A
Page 297 and 298:
Debug Access Port 4.12 APB Intercon
Page 299 and 300:
Debug Access Port Address width on
Page 301 and 302:
Debug Access Port 4.14 APB synchron
Page 303 and 304:
Debug Access Port 4.16 Authenticati
Page 305 and 306:
Chapter 5 ATB Interconnect Componen
Page 307 and 308:
ATB Interconnect Components Flushin
Page 309 and 310:
ATB Interconnect Components To alle
Page 311 and 312:
ATB Interconnect Components At an a
Page 313 and 314:
ATB Interconnect Components CLK AFV
Page 315 and 316:
ATB Interconnect Components Registe
Page 317 and 318:
ATB Interconnect Components • ATB
Page 319 and 320:
ATB Interconnect Components 5.4 ATB
Page 321 and 322:
ATB Interconnect Components CLK AFV
Page 323 and 324:
ATB Interconnect Components Table 5
Page 325 and 326:
ATB Interconnect Components Table 5
Page 327 and 328:
ATB Interconnect Components 5.6.4 S
Page 329 and 330:
Timestamp Components 6.1 About the
Page 331 and 332:
Timestamp Components The reset, RES
Page 333 and 334:
Timestamp Components Table 6-1 show
Page 335 and 336:
Timestamp Components • Encodes an
Page 337 and 338:
Timestamp Components 6.2.5 Narrow t
Page 339 and 340:
Timestamp Components • Decodes th
Page 341 and 342:
Chapter 7 Embedded Cross Trigger Th
Page 343 and 344:
Embedded Cross Trigger Interfaces h
Page 345 and 346:
Embedded Cross Trigger 7.2 ECT prog
Page 347 and 348:
Embedded Cross Trigger 7.4 ECT auth
Page 349 and 350:
Chapter 8 Trace Port Interface Unit
Page 351 and 352:
Trace Port Interface Unit 8.1.1 ATB
Page 353 and 354:
Trace Port Interface Unit 8.3 Misce
Page 355 and 356:
Trace Port Interface Unit The tie-o
Page 357 and 358:
Trace Port Interface Unit 8.6 Other
Page 359 and 360:
Trace Port Interface Unit 8.7 Authe
Page 361 and 362:
Trace Port Interface Unit Alternati
Page 363 and 364:
Trace Port Interface Unit 8.9.3 Sup
Page 365 and 366:
Trace Port Interface Unit 8.11 Exam
Page 367 and 368:
Trace Port Interface Unit Trigger s
Page 369 and 370:
Embedded Trace Buffer 9.1 About the
Page 371 and 372:
Embedded Trace Buffer Table 9-3 ETB
Page 373 and 374:
Embedded Trace Buffer 9.3 ETB trace
Page 375 and 376:
Embedded Trace Buffer 9.4 Flush ass
Page 377 and 378:
Embedded Trace Buffer 9.6 Write add
Page 379 and 380:
Embedded Trace Buffer 9.8 APB confi
Page 381 and 382:
Embedded Trace Buffer 9.10 Authenti
Page 383 and 384:
Chapter 10 Granular Power Requestor
Page 385 and 386:
Appendix A Signal Descriptions This
Page 387 and 388:
Signal Descriptions A.1.1 Serial wi
Page 389 and 390:
Signal Descriptions A.1.2 DAP bus i
Page 391 and 392:
Signal Descriptions Table A-4 DAP s
Page 393 and 394:
Signal Descriptions Table A-6 DAP A
Page 395 and 396:
Signal Descriptions Table A-7 DAP A
Page 397 and 398:
Signal Descriptions Table A-9 APB i
Page 399 and 400:
Signal Descriptions A.1.11 APB sync
Page 401 and 402:
Signal Descriptions Table A-12 ATB
Page 403 and 404:
Page 405 and 406:
Page 407 and 408:
Signal Descriptions A.3 Timestamp c
Page 409 and 410:
Signal Descriptions A.3.3 Narrow ti
Page 411 and 412:
Signal Descriptions A.3.6 Timestamp
Page 413 and 414:
Signal Descriptions A.4 Trigger com
Page 415 and 416:
Signal Descriptions Table A-26 CTM
Page 417 and 418:
Signal Descriptions Table A-27 TPIU
Page 419 and 420:
Signal Descriptions A.6 Authenticat
Page 421 and 422:
Signal Descriptions A.7 Granular po
Page 423 and 424:
Revisions Table B-2 Differences bet
show all

CoreSight SoC Technical Reference Manual - ARM Information Center

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?