CoreSight SoC Technical Reference Manual - ARM Information Center

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Functional Overview 2.4 Trigger components CoreSight SoC contains the following trigger components to control the logging of debug information: • Cross Trigger Interface. • Cross Trigger Matrix. The Cross Trigger Interface (CTI) and Cross Trigger Matrix (CTM) form the Embedded Cross Trigger (ECT) sub-system that enables the ARM Embedded Trace Macrocell (ETM) subsystems to interact, that is cross trigger, with each other. The main function of the ECT is to pass debug events from one processor to another. For example, the ECT can communicate debug state information from one processor to the others, so that you can stop the program execution on one or more processors at the same time if required. 2.4.1 Cross Trigger Interface The CTI combines and maps the trigger requests, and broadcasts them to all other interfaces on the ECT sub-system. When the CTI receives a trigger request it maps this onto a trigger output. This enables the ETM subsystems to cross trigger with each other. Figure 2-25 shows the external connections on the CTI. Block clock and reset APB clock and reset cticlk cticlken ctiresetn pclkdbg pclkendbg presetdbgn tisbypassin tisbypassack ctitrigin[7:0] ctitrigoutack[7:0] ctitrigout[7:0] ctitriginack[7:0] CTM link Trigger interface General control Sync by-pass control Handshake bypass Debug enable masking se ctiapbsbypass cisbypass asicctl[7:0] ctiapbsbypass[7:0] cisbypass[3:0] cihsbypass[3:0] tihsbypass[7:0] tinidensel[7:0] todbgensel[7:0] Cross Trigger Interface (CTI) ctichin[3:0] ctichoutack[3:0] ctichout[3:0] ctichinack[3:0] paddrdbg[11:2] pwritedbg pwdatadbg[31:0] pseldbg penabledbg pclkendbg paddrdbg31 prdatadbg[31:0] preadydbg Channel interface Optional APB port Figure 2-25 Cross Trigger Interface block diagram 2.4.2 Cross Trigger Matrix The CTM block controls the distribution of trigger requests. It connects to at least two CTIs and to other CTMs where required in a design. Figure 2-26 on page 2-19 shows the external connections on the CTM block. You must configure the CTM with the following parameter that defines the width of some ports of the block: • ECTCHANNELWIDTH. See CW in Figure 2-26 on page 2-19 where CW=ECTCHANNELWIDTH-1. ARM DDI 0480D Copyright © 2011, 2012 ARM. All rights reserved. 2-18 ID010213 Non-Confidential
Functional Overview Clock and reset Sync by-pass control Handshake bypass ctmclk ctmclken ctmresetn se cisbypass0 cisbypass1 cisbypass2 cisbypass3 cihsbypass0[CW:0] cihsbypass1[CW:0] cihsbypass2[CW:0] cihsbypass3[CW:0] Cross Trigger Matrix (CTM) ctmchin0[CW:0] ctmchoutack0[CW:0] ctmchout0[CW:0] ctmchinack0[CW:0] ctmchin1[CW:0] ctmchoutack1[CW:0] ctmchout1[CW:0] ctmchinack1[CW:0] ctmchin2[CW:0] ctmchoutack2[CW:0] ctmchout2[CW:0] ctmchinack2[CW:0] ctmchin3[CW:0] ctmchoutack3[CW:0] ctmchout3[CW:0] ctmchinack3[CW:0] Channel interface 0 Channel interface 1 Channel interface 2 Channel interface 3 Figure 2-26 Cross Trigger Matrix block diagram ARM DDI 0480D Copyright © 2011, 2012 ARM. All rights reserved. 2-19 ID010213 Non-Confidential
Page 1 and 2: CoreSight SoC Revision: r2p1 Techni
Page 3 and 4: Contents CoreSight SoC Technical Re
Page 5 and 6: 8.11 Example configuration scenario
Page 7 and 8: Preface About this book This is the
Page 9 and 10: Preface Clock HIGH to LOW Transient
Page 11 and 12: Preface Feedback ARM welcomes feedb
Page 13 and 14: Introduction 1.1 About CoreSight So
Page 15 and 16: Introduction 1.2 CoreSight SoC bloc
Page 17 and 18: Introduction 1.3 Typical CoreSight
Page 19 and 20: Chapter 2 Functional Overview This
Page 21 and 22: Functional Overview The SoC designe
Page 23 and 24: Functional Overview Clock and reset
Page 25 and 26: Functional Overview The following c
Page 27 and 28: Functional Overview 2.2 Advanced Tr
Page 29 and 30: Functional Overview Note In Figure
Page 33 and 34: Functional Overview The timestamp e
Page 35: Functional Overview Clock and reset
Page 41 and 42: Functional Overview 2.6.3 Event asy
Page 43 and 44: Chapter 3 Programmers Model This ch
Page 45 and 46: Programmers Model 3.2 Granular Powe
Page 47 and 48: Programmers Model 31 30 29 28 27 26
Page 49 and 50: Programmers Model Table 3-2 CPWRUPR
Page 51 and 52: Programmers Model 31 30 29 28 27 26
Page 53 and 54: Programmers Model Table 3-3 CPWRUPA
Page 55 and 56: Programmers Model Table 3-4 shows t
Page 57 and 58: Programmers Model 3.3.7 Lock Status
Page 59 and 60: Programmers Model Table 3-10 shows
Page 61 and 62: Programmers Model Table 3-13 shows
Page 63 and 64: Programmers Model 3.3.16 Peripheral
Page 65 and 66: Programmers Model 3.3.19 Component
Page 67 and 68: Programmers Model 3.4 APB interconn
Page 69 and 70: Programmers Model Table 3-24 ROM_EN
Page 71 and 72: Programmers Model 3.5.5 Peripheral
Page 73 and 74: Programmers Model 3.5.8 Component I
Page 75 and 76: Programmers Model Figure 3-32 shows
Page 77 and 78: Programmers Model 3.7 ATB funnel re
Page 79 and 80: Programmers Model Table 3-36 Ctrl_R
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Programmers Model 3.7.6 Integration
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Programmers Model Table 3-43 shows
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Programmers Model 3.7.14 Device Typ
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Programmers Model 31 8 7 0 Reserved
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Programmers Model 31 8 7 4 3 0 Rese
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Programmers Model 3.9 ATB replicato
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Programmers Model 3.9.7 Claim Tag C
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Programmers Model 3.9.10 Authentica
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Programmers Model 3.9.13 Peripheral
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Programmers Model Usage constraints
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Programmers Model Table 3-83 ETB re
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Programmers Model to determine the
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Programmers Model 3.11.8 ETB RAM Wr
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Programmers Model 31 14 13 12 11 10
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Programmers Model 3.11.12 Integrati
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Programmers Model Table 3-97 ITATBD
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Programmers Model 31 8 7 6 5 4 3 2
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Programmers Model 3.11.26 Periphera
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Programmers Model Offset Name Type
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Programmers Model Bits Name Functio
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Programmers Model 3.13.14 CTI Chann
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Programmers Model 3.13.17 CTI Chann
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Programmers Model Bits Name Functio
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Programmers Model 3.13.26 Enable CT
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Programmers Model Figure 3-142 show
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Programmers Model Attributes See th
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Programmers Model 3.13.40 Lock Stat
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Programmers Model Table 3-167 PIDR2
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Programmers Model 3.13.52 Component
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Programmers Model 3.14 TPIU registe
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Programmers Model 3.15 TPIU registe
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Programmers Model Table 3-174 Suppo
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Programmers Model Table 3-174 Suppo
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Programmers Model Table 3-175 Curre
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Programmers Model Table 3-175 Curre
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Programmers Model Configurations Th
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Programmers Model Note ARM recommen
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Programmers Model inserted during n
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Programmers Model Table 3-189 ITATB
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Programmers Model 31 8 7 6 5 4 3 2
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Programmers Model 3.15.31 Periphera
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Programmers Model 3.15.34 Component
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Programmers Model Table 3-212 AHB-A
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Programmers Model Table 3-216 JTAG-
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Programmers Model Table 3-217 JTAG-
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Programmers Model 3.17.2 AHB-AP reg
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Programmers Model AHB-AP Data Read/
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Programmers Model 31 30 28 27 24 23
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Programmers Model AXI-AP Data RW Re
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Programmers Model AXI-AP Debug Base
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Programmers Model • APB-AP Banked
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Programmers Model APB-AP Data Read/
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Programmers Model Accesses to this
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Programmers Model the APnDP bit = 0
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Programmers Model 31 24 23 8 7 4 3
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Programmers Model SW-DP only 31 10
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Programmers Model • Accessed by a
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Programmers Model Table 3-251 Times
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Programmers Model 31 1 0 RESERVED R
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Debug Access Port 4.1 About the Deb
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Debug Access Port APB-Multiplexer A
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Debug Access Port DAP internal bus
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Debug Access Port to continually re
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Debug Access Port The SW-DP clock,
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Debug Access Port Figure 4-7 shows
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Debug Access Port Table 4-4 TARGETI
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Debug Access Port 4.3 DAPBUS interc
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Debug Access Port 4.5 DAP synchrono
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Debug Access Port In this way, the
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Debug Access Port 4.8 JTAG-AP The J
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Debug Access Port 4.9 AXI-AP The AX
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Debug Access Port Similarly, after
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Debug Access Port Unaligned accesse
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Debug Access Port 4.10 AHB-AP The A
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Debug Access Port • Packed transf
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Debug Access Port 4.11 APB-AP The A
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Debug Access Port 4.12 APB Intercon
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Debug Access Port Address width on
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Debug Access Port 4.14 APB synchron
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Debug Access Port 4.16 Authenticati
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Chapter 5 ATB Interconnect Componen
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ATB Interconnect Components Flushin
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ATB Interconnect Components To alle
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ATB Interconnect Components At an a
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ATB Interconnect Components CLK AFV
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ATB Interconnect Components Registe
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ATB Interconnect Components • ATB
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ATB Interconnect Components 5.4 ATB
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ATB Interconnect Components CLK AFV
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ATB Interconnect Components Table 5
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ATB Interconnect Components Table 5
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ATB Interconnect Components 5.6.4 S
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Timestamp Components 6.1 About the
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Timestamp Components The reset, RES
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Timestamp Components Table 6-1 show
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Timestamp Components • Encodes an
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Timestamp Components 6.2.5 Narrow t
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Timestamp Components • Decodes th
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Chapter 7 Embedded Cross Trigger Th
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Embedded Cross Trigger Interfaces h
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Embedded Cross Trigger 7.2 ECT prog
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Embedded Cross Trigger 7.4 ECT auth
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Chapter 8 Trace Port Interface Unit
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Trace Port Interface Unit 8.1.1 ATB
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Trace Port Interface Unit 8.3 Misce
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Trace Port Interface Unit The tie-o
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Trace Port Interface Unit 8.6 Other
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Trace Port Interface Unit 8.7 Authe
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Trace Port Interface Unit Alternati
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Trace Port Interface Unit 8.9.3 Sup
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Trace Port Interface Unit 8.11 Exam
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Trace Port Interface Unit Trigger s
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Embedded Trace Buffer 9.1 About the
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Embedded Trace Buffer Table 9-3 ETB
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Embedded Trace Buffer 9.3 ETB trace
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Embedded Trace Buffer 9.4 Flush ass
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Embedded Trace Buffer 9.6 Write add
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Embedded Trace Buffer 9.8 APB confi
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Embedded Trace Buffer 9.10 Authenti
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Chapter 10 Granular Power Requestor
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Appendix A Signal Descriptions This
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Signal Descriptions A.1.1 Serial wi
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Signal Descriptions A.1.2 DAP bus i
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Signal Descriptions Table A-4 DAP s
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Signal Descriptions Table A-6 DAP A
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Signal Descriptions Table A-7 DAP A
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Signal Descriptions Table A-9 APB i
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Signal Descriptions A.1.11 APB sync
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Signal Descriptions Table A-12 ATB
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Signal Descriptions A.3 Timestamp c
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Signal Descriptions A.3.3 Narrow ti
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Signal Descriptions A.3.6 Timestamp
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Signal Descriptions A.4 Trigger com
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Signal Descriptions Table A-26 CTM
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Signal Descriptions Table A-27 TPIU
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Signal Descriptions A.6 Authenticat
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Signal Descriptions A.7 Granular po
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Revisions Table B-2 Differences bet
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