CoreSight SoC Technical Reference Manual - ARM Information Center

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Programmers Model 31 8 7 4 3 0 Reserved REVAND CMOD Figure 3-17 PIDR3 bit assignments Table 3-18 shows the bit assignments. Table 3-18 PIDR3 bit assignments Bits Name Function [31:8] Reserved - [7:4] REVAND Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is zero. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to zero. 0b0000 Indicates that there are no errata fixes to this component. [3:0] CMOD Indicates whether the customer has modified the behavior of the component. In most cases, this field is zero. The customer changes this value on modifications to this component. 0b0000 Indicates that the customer has not modified this component. 3.3.18 Component ID0 Register The CIDR0 characteristics are: Purpose A component identification register that indicates the identification registers are present. Usage constraints There are no usage constraints. Configurations This register is available in all configurations. Attributes See the register summary in Table 3-1 on page 3-3. Figure 3-18 shows the bit assignments. 31 8 7 0 Reserved PRMBL_0 Figure 3-18 CIDR0 bit assignments Table 3-19 shows the bit assignments. Table 3-19 CIDR0 bit assignments Bits Name Function [31:8] Reserved - [7:0] PRMBL_0 Contains bits[7:0] of the component identification code. 0x0D Bits[7:0] of the identification code. ARM DDI 0480D Copyright © 2011, 2012 ARM. All rights reserved. 3-22 ID010213 Non-Confidential
Programmers Model 3.3.19 Component ID1 Register The CIDR1 characteristics are: Purpose A component identification register that indicates the identification registers are present. This register also indicates the component class. Usage constraints There are no usage constraints. Configurations This register is available in all configurations. Attributes See the register summary in Table 3-1 on page 3-3. Figure 3-19 shows the bit assignments. 31 8 7 4 3 0 Reserved CLASS PRMBL_1 Figure 3-19 CIDR1 bit assignments Table 3-20 shows the bit assignments. Table 3-20 CIDR1 bit assignments Bits Name Function [31:8] Reserved - [7:4] CLASS Class of the component. Indicates, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code. 0b1001 Indicates that the component is a CoreSight component. [3:0] PRMBL_1 Contains bits[11:8] of the component identification code. 0b0000 Bits[11:8] of the identification code. 3.3.20 Component ID2 Register The CIDR2 characteristics are: Purpose A component identification register, that indicates the identification registers are present. Usage constraints There are no usage constraints. Configurations This register is available in all configurations. Attributes See the register summary in Table 3-1 on page 3-3. Figure 3-20 shows the bit assignments. 31 8 7 0 Reserved PRMBL_2 Figure 3-20 CIDR2 bit assignments ARM DDI 0480D Copyright © 2011, 2012 ARM. All rights reserved. 3-23 ID010213 Non-Confidential
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CoreSight SoC Revision: r2p1 Techni
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Contents CoreSight SoC Technical Re
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8.11 Example configuration scenario
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Preface About this book This is the
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Preface Clock HIGH to LOW Transient
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Preface Feedback ARM welcomes feedb
Page 13 and 14: Introduction 1.1 About CoreSight So
Page 15 and 16: Introduction 1.2 CoreSight SoC bloc
Page 17 and 18: Introduction 1.3 Typical CoreSight
Page 19 and 20: Chapter 2 Functional Overview This
Page 21 and 22: Functional Overview The SoC designe
Page 23 and 24: Functional Overview Clock and reset
Page 25 and 26: Functional Overview The following c
Page 27 and 28: Functional Overview 2.2 Advanced Tr
Page 29 and 30: Functional Overview Note In Figure
Page 33 and 34: Functional Overview The timestamp e
Page 41 and 42: Functional Overview 2.6.3 Event asy
Page 43 and 44: Chapter 3 Programmers Model This ch
Page 45 and 46: Programmers Model 3.2 Granular Powe
Page 47 and 48: Programmers Model 31 30 29 28 27 26
Page 49 and 50: Programmers Model Table 3-2 CPWRUPR
Page 51 and 52: Programmers Model 31 30 29 28 27 26
Page 53 and 54: Programmers Model Table 3-3 CPWRUPA
Page 55 and 56: Programmers Model Table 3-4 shows t
Page 57 and 58: Programmers Model 3.3.7 Lock Status
Page 59 and 60: Programmers Model Table 3-10 shows
Page 63: Programmers Model 3.3.16 Peripheral
Page 67 and 68: Programmers Model 3.4 APB interconn
Page 69 and 70: Programmers Model Table 3-24 ROM_EN
Page 71 and 72: Programmers Model 3.5.5 Peripheral
Page 73 and 74: Programmers Model 3.5.8 Component I
Page 75 and 76: Programmers Model Figure 3-32 shows
Page 77 and 78: Programmers Model 3.7 ATB funnel re
Page 79 and 80: Programmers Model Table 3-36 Ctrl_R
Page 81 and 82: Programmers Model Table 3-37 Priori
Page 83 and 84: Programmers Model Attributes See th
Page 85 and 86: Programmers Model Table 3-38 ITATBD
Page 87 and 88: Programmers Model 3.7.6 Integration
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Page 95 and 96: Programmers Model 31 8 7 0 Reserved
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Page 109 and 110: Programmers Model 3.9.10 Authentica
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Programmers Model Usage constraints
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Programmers Model Table 3-82 shows
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Programmers Model Table 3-83 ETB re
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Programmers Model to determine the
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Programmers Model 3.11.8 ETB RAM Wr
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Programmers Model 31 14 13 12 11 10
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Programmers Model 3.11.12 Integrati
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Programmers Model Table 3-97 ITATBD
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Programmers Model 31 8 7 6 5 4 3 2
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Programmers Model 3.11.26 Periphera
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Programmers Model 31 8 7 4 3 0 Rese
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Programmers Model Offset Name Type
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Programmers Model 31 8 7 0 Reserved
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Programmers Model Bits Name Functio
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Programmers Model 3.13.14 CTI Chann
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Programmers Model 3.13.17 CTI Chann
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Programmers Model Bits Name Functio
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Programmers Model 3.13.26 Enable CT
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Programmers Model Figure 3-142 show
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Programmers Model Attributes See th
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Programmers Model 3.13.40 Lock Stat
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Programmers Model Table 3-167 PIDR2
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Programmers Model 3.13.52 Component
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Programmers Model 3.14 TPIU registe
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Programmers Model 3.15 TPIU registe
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Programmers Model Table 3-174 Suppo
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Programmers Model Table 3-174 Suppo
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Programmers Model Table 3-175 Curre
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Programmers Model Table 3-175 Curre
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Programmers Model Configurations Th
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Programmers Model Note ARM recommen
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Programmers Model inserted during n
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Programmers Model Table 3-189 ITATB
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Programmers Model 31 8 7 6 5 4 3 2
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Programmers Model 3.15.31 Periphera
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Programmers Model 3.15.34 Component
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Programmers Model Table 3-212 AHB-A
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Programmers Model Table 3-216 JTAG-
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Programmers Model Table 3-217 JTAG-
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Programmers Model 3.17.2 AHB-AP reg
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Programmers Model AHB-AP Data Read/
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Programmers Model 31 30 28 27 24 23
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Programmers Model AXI-AP Data RW Re
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Programmers Model AXI-AP Debug Base
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Programmers Model • APB-AP Banked
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Programmers Model APB-AP Data Read/
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Programmers Model Accesses to this
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Programmers Model the APnDP bit = 0
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Programmers Model 31 24 23 8 7 4 3
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Programmers Model SW-DP only 31 10
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Programmers Model • Accessed by a
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Programmers Model Table 3-251 Times
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Programmers Model 31 1 0 RESERVED R
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Programmers Model 3.19.6 Peripheral
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Programmers Model 3.19.9 Peripheral
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Debug Access Port 4.1 About the Deb
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Debug Access Port APB-Multiplexer A
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Debug Access Port DAP internal bus
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Debug Access Port to continually re
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Debug Access Port The SW-DP clock,
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Debug Access Port Figure 4-7 shows
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Debug Access Port Table 4-4 TARGETI
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Debug Access Port 4.3 DAPBUS interc
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Debug Access Port 4.5 DAP synchrono
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Debug Access Port In this way, the
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Debug Access Port 4.8 JTAG-AP The J
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Debug Access Port 4.9 AXI-AP The AX
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Debug Access Port Similarly, after
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Debug Access Port Unaligned accesse
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Debug Access Port 4.10 AHB-AP The A
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Debug Access Port • Packed transf
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Debug Access Port 4.11 APB-AP The A
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Debug Access Port 4.12 APB Intercon
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Debug Access Port Address width on
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Debug Access Port 4.14 APB synchron
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Debug Access Port 4.16 Authenticati
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Chapter 5 ATB Interconnect Componen
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ATB Interconnect Components Flushin
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ATB Interconnect Components To alle
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ATB Interconnect Components At an a
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ATB Interconnect Components CLK AFV
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ATB Interconnect Components Registe
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ATB Interconnect Components • ATB
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ATB Interconnect Components 5.4 ATB
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ATB Interconnect Components CLK AFV
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ATB Interconnect Components Table 5
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ATB Interconnect Components Table 5
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ATB Interconnect Components 5.6.4 S
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Timestamp Components 6.1 About the
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Timestamp Components The reset, RES
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Timestamp Components Table 6-1 show
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Timestamp Components • Encodes an
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Timestamp Components 6.2.5 Narrow t
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Timestamp Components • Decodes th
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Chapter 7 Embedded Cross Trigger Th
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Embedded Cross Trigger Interfaces h
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Embedded Cross Trigger 7.2 ECT prog
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Embedded Cross Trigger 7.4 ECT auth
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Chapter 8 Trace Port Interface Unit
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Trace Port Interface Unit 8.1.1 ATB
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Trace Port Interface Unit 8.3 Misce
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Trace Port Interface Unit The tie-o
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Trace Port Interface Unit 8.6 Other
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Trace Port Interface Unit 8.7 Authe
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Trace Port Interface Unit Alternati
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Trace Port Interface Unit 8.9.3 Sup
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Trace Port Interface Unit 8.11 Exam
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Trace Port Interface Unit Trigger s
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Embedded Trace Buffer 9.1 About the
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Embedded Trace Buffer Table 9-3 ETB
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Embedded Trace Buffer 9.3 ETB trace
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Embedded Trace Buffer 9.4 Flush ass
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Embedded Trace Buffer 9.6 Write add
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Embedded Trace Buffer 9.8 APB confi
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Embedded Trace Buffer 9.10 Authenti
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Chapter 10 Granular Power Requestor
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Appendix A Signal Descriptions This
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Signal Descriptions A.1.1 Serial wi
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Signal Descriptions A.1.2 DAP bus i
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Signal Descriptions Table A-4 DAP s
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Signal Descriptions Table A-6 DAP A
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Signal Descriptions Table A-7 DAP A
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Signal Descriptions Table A-9 APB i
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Signal Descriptions A.1.11 APB sync
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Signal Descriptions Table A-12 ATB
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Signal Descriptions A.3 Timestamp c
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Signal Descriptions A.3.3 Narrow ti
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Signal Descriptions A.3.6 Timestamp
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Signal Descriptions A.4 Trigger com
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Signal Descriptions Table A-26 CTM
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Signal Descriptions Table A-27 TPIU
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Signal Descriptions A.6 Authenticat
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Signal Descriptions A.7 Granular po
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Revisions Table B-2 Differences bet
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