CoreSight SoC Technical Reference Manual - ARM Information Center

Functional Overview
The AMBA-compliant LPI is optional on the DAP synchronous bridge.
DAP synchronous bridge
Clock
and
reset
dapclk
dapclens
dapresetn
dapclkenm
dapwrites
dapwdatas[31:0]
dapaddrs[31:0]
dapreadys
dapenables
dapsels
dapaborts
dapslverrs
daprdatas[31:0]
Slave
interface
Master
interface
dapwritem
dapwdatam[31:0]
dapaddrm[31:0]
dapreadym
dapenablem
dapselm
dapabortm
dapslverrm
daprdatam[31:0]
Figure 2-4 DAP synchronous bridge block diagram
2.1.5 JTAG - Access Port
The JTAG-AP provides a dedicated on-chip JTAG access to components from the DAP,
independent of the off-chip JTAG or SW connection. See Chapter 4 Debug Access Port for more
information.
Figure 2-5 shows the external connections on the JTAG-AP.
Clock
and
reset
Debug
access
port
dapclk
dapclken
dapresetn
dapwrite
dapwdata[31:0]
dapabort
dapready
dapenable
dapsel
daprdata[31:0]
dapaddr[7:2]
JTAG-AP
csrtck[7:0]
srstconnected[7:0]
portconnected[7:0]
portenabled[7:0]
cstdo[7:0]
nsrstout[7:0]
ncstrst[7:0]
cstck[7:0]
cstdi[7:0]
cstms[7:0]
Connections
to JTAG
slave
Figure 2-5 JTAG-Access Port block diagram
2.1.6 Advanced eXtensible Interface - Access Port
The Advanced eXtensible Interface - Access Port (AXI-AP) connects a DAP to an AXI
component or system.
You must configure the AXI-AP during implementation, with the following parameters:
• AXI_ADDR_WIDTH, 32-bit or 64-bit. See aw in Figure 2-6 on page 2-5.
• AXI_DATA_WIDTH, 32-bit or 64-bit. See dw in Figure 2-6 on page 2-5.
See Chapter 4 Debug Access Port for more information.
Figure 2-6 on page 2-5 shows the external connections on the AXI-AP.
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