industry news - Chip Scale Review

More documents

Recommendations

Info

14 Chip Scale Review ■ March 2007 ■ [ChipScaleReview.com]
INDUSTRY NEWS APEX Continued from page 13 >> exhibit unless you’re selling to the folks who make, sell or buy PWBs. As I made my rounds, the comments were mixed, but generally favorable about the show. Most of the people I spoke to thought the show was much smaller this year. Not so! said Anna Garrido, the IPC’s marketing and communications lady, when I questioned her in the press room. During the three-day run of exhibits, floor traffic was modest on Tuesday and Wednesday and slowed to a trickle on the third and final day. It would not be a challenge for most people to cover all exhibits in one day. According to a 2006 IPC news release, some 14,967 square meters (161,000 square feet) of the Convention Center were expected to be occupied by exhibitors. Attendance figures were not were not forthcoming by our deadline, two weeks after the show. In fact, she reported, this year’s APEX boasted more exhibitors and more overall exhibit space than the prior year. It didn’t seem like it to me or almost everyone else I talked to. Perhaps it was the lack of skyscraper exhibits which Booth arrangements presented a clear “line-ofsight” from one end of the hall to the other. we’ve come to expect, with their cantilevered rooftops and meeting rooms on second or third levels. Could the problem be the location— The Los Angeles Convention Center that dominates two massive city blocks in downtown Smogville. Fourth Location This was the fourth location for APEX since its first show in 2000. The Printed Circuits Expo, which was initially a separate event, was joined at the shoulder to APEX in 2004. In 2000, NEPCON West ran a bifurcated show in Anaheim, about two weeks before APEX. And then NEPCON West ran out of steam as the IPC cut NEPCON’s excessive exhibiting prices by half. Continued on page 26 >> Intel Continued from page 13 >> However, the research is instrumental in investigating new innovations in individual or specialized processor or core functions, the types of chip-to-chip and chip-to-computer interconnects required, and—most importantly—how software will need to be designed to leverage multiple processor cores most efficiently. Power Cores On/Off The research also investigated methods to power cores on and off independently, so only the ones needed to complete a task are used, providing more energy efficiency. Further research will focus on the addition of 3-D stacked memory to the chip. The Tera-scale program has over 100 projects. ASCI Red, the first computer to benchmark at a Teraflops in 1996, used nearly 10,000 Pentium Pro CPUs. Teraflop performance was first achieved in 1996, on the ASCI Red Supercomputer built by Intel for Sandia National Laboratory. That computer occupied more than 186 square meters, was powered by nearly 10,000 Pentium Pro processors, and consumed over 500kW. [intel.com] ■ Chip Scale Review ■ March 2007 ■ [ChipScaleReview.com] 15
Page 1 and 2: ChipScale® www.ChipScaleReview.com
Page 3: CONTENTS The International Magazine
Page 6 and 7: Technologies, Inc. Your Global Prov
Page 9 and 10: ASSEMBLY LINES Farewell to Two Rema
Page 11 and 12: plasma cleaning solutions With prod
Page 13 and 14: Now, some of you may say, “Hey, P
Page 15: INDUSTRY NEWS APEX 2007 Los Angeles
Page 19 and 20: INDUSTRY NEWS As usual, Panasonic
Page 21: INDUSTRY NEWS IBM and Intel Continu
Page 24 and 25: INDUSTRY NEWS SEMICONDUCTORS AND TH
Page 26 and 27: INDUSTRY NEWS Mirrored Pinouts Cont
Page 28 and 29: INDUSTRY NEWS APEX Continued from p
Page 30 and 31: Are Wire Bonders Running Out of Ste
Page 32 and 33: “some of which are promising. “
Page 34: The Eagle 60AP is ASM Pacific’s e
Page 37 and 38: For more information on any adverti
Page 39 and 40: Laurier's M9 flip-chip die bonder T
Page 41 and 42: NM-5850A die bonder from Panasonic
Page 43 and 44: Close-ups of a 300mm silicon test w
Page 45 and 46: For more information on any adverti
Page 47 and 48: The Challenge of Packaging Small Po
Page 49 and 50: Figure 1. This figure illustrates t
Page 51 and 52: Figure 3. This is a next-generation
Page 53 and 54: For a 150mm wafer with dice of 6mm
Page 55 and 56: High-Speed Stencil Cleaning Techniq
Page 57: keep a larger proportion of the pap
Page 60 and 61: INDEX TO 2006 ARTICLES Note: You ma
Page 62 and 63: Camtek’s New Falcon 600 AOI Syste
Page 64 and 65: BACK OF THE BOOK 5 Critical Challen
Page 66:
INDUSTRY NEWS Worldwide Silicon Shi
show all

industry news - Chip Scale Review

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?