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INDUSTRY NEWS IBM and Intel Continued from page 13 >> High-k + Metal Gate Transistors Metal Gate • Increases the gate field effect High-k Dielectric • Increases the gate field effect • Allows use of thicker dielectric layer to reduce gate leakage HK + MG Combined • Drive current increased >20% (>20% higher performance) • Or source-drain leakage reduced >5x • Gate oxide leakage reduced >10x S HK+MG Transistor Silicon Substrate Low resistance layer Metal gate Different for NMOS and PMOS High-k gate oxide Hafnium based D combined: The problems are Fermilevel pinning and “phonon scattering.” Joint Development IBM’s work has been conducted jointly with Sony, Toshiba and Intel’s arch nemisis AMD. IBM says it has already “inserted” the technology into its East Fishkill, N.Y., fab and will begin to produce ICs at 45nm beginning next year. This technology, termed “high-k metal gate,” substitutes a material in place of Si, although the material type was not disclosed. [ibm.com] [intel.com] ■ This graphic, based on Intel-supplied information, illustrates the company’s 45nm High-k + metal gate transistor. Next-Generation CPUs Intel says the process will be employed in its next-generation of Core 2 CPUs— already in house—the first of at least 15 45nm processor products in development at the company. The development, Intel adds, will enable “record speeds,” while reducing electrical leakage that can adversely affect power consumption, noise and costs. It will also ensure that Moore’s Law “will thrive well into the next decade,” the microprocessor leader claims. Intel says it is using a new material combination of high-k gate dielectrics and metal gates. The company will begin production of the first 45nm CPU (Penryn) in the second half of this year. Intel Beating the Competition Its development is more than a year ahead of its competitors, Intel claims. In its 45nm technology, Intel has employed a hafnium-based, high-k material in the gate dielectric. The dielectric is created with atomic layer deposition (ALD), where a single layer of the high-k material molecule is deposited at a time. Because the high-k gate dielectric is not compatible with current Si gate electrodes, Intel said it had to develop the new metal gate materials to solve two problems that arise when the two are CORWIL is the leader in wafer backgrinding, wafer dicing and visual inspection to commercial, military and medical specs. CORWIL’s newest addition in dicing equipment is a fully automatic, latest state-of-the-art 12 inch dicing saw that strengthens CORWIL’s technical leadership for chip-free and fast turn-around dicing. CORWIL dices Si, GaAs, Sapphire, SiGe, laminates and many other materials and CORWIL is unsurpassed in IC assembly in ceramic, BGA, flip-chip, and MLF/QFN type packages. ➢ High Volume — Millions of dice per month ➢ Automatic High-Speed Pick-and-Place ➢ Automatic Vision Inspection Systems ➢ Low K, MEMS and Optical/Imaging wafers processed ➢ Experts in Multi-die Type Wafer dicing ➢ Highest Quality and Best Service in the Industry Since 1990 CORWIL has built its reputation providing customers with: Excellent Quality and Superior Service Contact Us At: CORWIL Technology Corporation 1635 McCarthy Blvd. Milpitas, CA 95035 info@corwil.com Tel: 408-321-6404 www.corwil.com Fax: 408-321-6407 ISO 9001:2000 Registered DSCC QML Certification MIL-PRF-38535 MIL-STD-883 Chip Scale Review ■ March 2007 ■ [ChipScaleReview.com] 19
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Page 9 and 10: ASSEMBLY LINES Farewell to Two Rema
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