industry news - Chip Scale Review

ChipScale® 

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r e v i e w 

March 2007 

• Flip-Chip and Die-Attach Trends 

• Wire Bonders

One Stop Wafer Bumping & WLCSP with UAT 

Wafer Level Chipscale Package 

Wafer Bumping Services 

Gold Bumps 

Bump Height typically ranges from 2 to 25 microns and bump pitch may go as 

low as 35 micons 

Copper Pillar Bumps 

Copper pillar bumps with solder cap of either SnAg or pure Sn for fine pitch 

application. Bump pitch may go as low as 100 microns. Typical bump height is 

65 microns of copper pillar with 20 microns of solder cap. 

Small Solder Bumps 

Electroplated solder bumps either of SnAg or pure Sn fr fine pitch application. 

Bump height typically ranges between 25 to 100 microns. Bump pitch may go 

as low as 100 microns for lower bump heights. 

Large Solder Bumps 

Ball drop and ‘reflow’ bump height ranges between 150 to 350 microns 

depending on diameter or Under-bump metallization and solder ball size being 

used. Typical solder bump composition is SnAgCu (3.0% Ag and 0.5% Cu) 

Repassivation & pad redistribution 

Polymide or Bensocyclobutene as the repassivation layer for enhancing the 

performance and reliability of wafer-level packaging redistribution of bond pads 

into matric arrays to cater for devices not currently designed for wafer bumping. 

• Backgrind 

• Laser Mask 

• Test 

• Singulation 

• Inspection 

• Tape & Reel 

• Qualification Reports 

available at this time 

Unisem-Advanpack Technologies Sdn Bhd (*UAT*), a joint venture between Unisem (M) Berhad (“Unsiem”) and Advanpack 

Solutions Pte Ltd., located in Ipoh, Malaysia, is one of the first independent wafer bumping service providers in Malaysia. 

At UAT we offer a one-stop center for wafer bumping services which includes gold bumps, electroplated solder bumps 

through “ball drop” process. We also offer pad redistribution and repassivation for wafer sizes of 4, 6 and 8-inch diameter. 

Unisem Europe Ltd. 

Bernard Ramsay 

European Sales Director 

Parkway, Pen-y-fan Industrial Estate 

Crumlin 

South Wales NP11 3XT 

Bernie.Ramsay@Unisem-eu.com 

Cell/Mobile +44 (0)7779 657696 

Unisem USA 

Mike Stokman 

North American VP of Sales 

Unisem USA 

1893 Klondike Road 

Livermore 

CA 94550 

Mike.stokman@unisem-us.com 

Cell/Mobile + 925 980 6515

CONTENTS 

The International Magazine of Chip-Scale 

Electronics, Flip-Chip Technology, Optoelectronics 

Interconnection and Wafer-Level Packaging 

March 2007 

Volume 11, Number 2 

THE COVER 

Someone (was it old Will Shakespeare, again?) 

once said, “There’s nothing new under the sun.” 

We beg to differ! There’s lots new, especially in the 

machines that are used to package the chips we all 

love (and either directly or indirectly profit from). 

Over the past few years, we’ve seen a consolidation 

in the sub-industries that make wire bonders and die 

attach. It’s been less than two years since pioneer 

Kulicke & Soffa Industries sold its wedge bonding 

product line to Orthodyne, probably a smart move 

for both. And almost while we weren’t looking, The 

former ESEC, after becoming a Unaxis brand, 

became an Oerliken brand! 

Editor Ron Iscoff looks at the good and bad of today’s 

wire bonders, and Orthodyne chips in with a new 

ribbon bonding process. Meanwhile, Terry Thompson, 

our senior editor from the cold climes of the Midwest, 

shook off the snow long enough to report on 

machines for die attach and flip-chip packaging. 

(Illustration for Chip Scale Review by 

Design 2 Market) [design2marketinc.com] 

COVER FEATURES 

Are Wire Bonders Running Out of Steam? 28 

How this Essential IC Assembly Tool Is Keeping Pace 

Ron Iscoff, Editor 

Wire bonders are becoming smarter, faster and more cost-effective on 

the assembly line. In the bonder’s 50+ year history, the machines have 

become not only the icon for IC assembly, but the most-needed tool at 

every IC assembler. Is there room for improvement? Of course, and 

we’ll explore that topic in this article. 

International Directory of Production Wire Bonders 

Chip Scale Review Staff 

34 

Flip-Chip Processing Secrets: 

36 

Saving Money and Saving Time 

Terrence E. Thompson, Senior Editor 

The biggest “secret” to successful, automated flip-chip production is 

the careful selection of the increasingly intelligent equipment that makes 

the technology more affordable, reliable and amazingly accurate. Your 

choice of the best tools for your applications is going to result in your 

company either saving lots of money, or—alternatively—writing a 

check for a dust-gathering behemoth that spends much of its time 

sitting in a corner like a wallflower at the prom. 

International Directory of Flip Chip & Die Attach Bonders/Aligners 

Chip Scale Review Staff 

43 

The Challenge of Packaging Small Power Devices 45 

Dr. Christoph Luechinger and Siegbert Haumann, 

Orthodyne Electronics Corp. 

Until recently, fine wire ball bonding and Cu strap attachment were the 

main interconnect techniques for power semiconductors smaller than the 

TO-252. A new, large aluminum ribbon bonding process, however, has 

overcome past size restrictions, enabling the use of this technology to 

overcome weaknesses in traditional approaches. 

CONTINUED >> 

Chip Scale Review, at 7291 Coronado Dr., Suite 8, San Jose, CA 95129 

(ISSN 1526-1344), is published eight times a year, with issues in 

January-February, March, April, May-June, July, August-September, 

October and November-December. 

Periodical postage paid at San Jose, Calif., and additional offices. 

POSTMASTER: Send address changes to Chip Scale Review magazine, 

7291 Coronado Dr., Suite 8, San Jose, CA 95129. 

Chip Scale Review ■ March 2007 ■ [ChipScaleReview.com] 1

CONTENTS 

FEATURE ARTICLE 

High-Speed Stencil Cleaning Techniques for IC 53 

Substrate-Level Assembly Lower Total Costs 

Trevor Warren, DEK 

Printing-type processes have quickly earned acceptance 

in semiconductor and other sophisticated packaging 

applications. Stencil printing is an enabling technology 

for many wafer-bumping and similar uses. Integrating 

proven, innovative stencil cleaning process improvements 

into operations, for example, is a very efficient 

way for companies to control costs and improve yields. 

LATE NEWS 

STATS ChipPAC Joins Billion-Dollar-Buyout Club 

Singapore—Less than four months after the Carlyle Group bid $5.4 billion 

for Advanced Semiconductor Engineering, Taiwan, a Singapore group has 

offered to buy out STATS ChipPAC’s available unowned shares for cash. 

In late February, Temasek Holdings Pte., Singapore’s state-owned investment 

company, offered up to $1.6 billion for all remaining shares of the Singaporebased 

IC assembly and test provider. Temasek’s wholly-owed subsidiary 

Singapore Technologies Semiconductors Pte. currently owns 35.6 percent of 

STATS ChipPAC. [statschippac.com] 

DEPARTMENTS 

Publisher’s Letter Gene Selven 

We’re counting our ABCs for you! 

Assembly Lines Ron Iscoff 

Farewell to two remarkable leaders 

Standards Mark Bird 

Package-on-Package is ready to take-off 

Test Patterns Paul M. Sakamoto 

The ‘mainframe mentality’ lives on! 

Industry News 

Calendar 

WLCSP Forum Manuel H. Mere 

Ongoing migration to finer WLCSP pitches 

Inside Patents A. Jason Mirabito and Carol Peters 

Underfill: patent offers a new approach to an old problem 

Index to 2006 Articles 

What’s New! 

Back of the Book Dr. David Tuckerman 

5 critical challenges for 3D packaging 

Ad Index/More News/Sales Offices 

5 

7 

8 

10 

13 

21 

52 

57 

58 

60 

62 

64 


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VOLUME 11, NUMBER 2 

The International Magazine of Chip-Scale 

Electronics, Flip-Chip Technology, Optoelectronic 

Interconnection and Wafer-Level Packaging 

STAFF 

Gene Selven Publisher 

7291 Coronado Dr., Ste. 8, San Jose, CA 95129 

b 408.996.7016 > 408.996.7871 

gselven@aol.com 

Ron Iscoff Editor & Associate Publisher 

929 Ebbetts Ave., Manteca, CA 95337 

b 209.824.1289 > 209.644.7747 

chipscale@gmail.com 

Terrence Thompson Senior Editor 

2303 Randall Rd. #140, Carpentersville, IL 60110 

b 847.515.1255 

tethompson@aol.com 

Steve Berry Contributing Editor 

b 408.369.7000 > 408.369.8021 

saberry@electronictrendpubs.com 

Dr. Tom Di Stefano Contributing Editor 

b 408.399.4501 > 408.395.0448 

tom@centipedesystems.com 

Dr. Subash Khadpe Contributing Editor 

skhadpe@semitech.com 

Harvey S. Miller Contributing Editor-at-Large 

b 650.328.4550 > 650.327.2360 

h.miller@ieee.org 

Paul M. Sakamoto Contributing Editor–Test 

b 925.924.9110 x148 

paul.sakamoto@inovys.com 

Sandra Winkler Contributing Editor 

b 408.369.7000 > 408.369.8021 

slwinkler@electronictrendpubs.com 

The Official Publication of the WLCSP Forum 

SUBSCRIPTION INQUIRIES 

Judy Levin Chip Scale Review 


b 408.996.7016 > 408.996.7871 

csrsubs@chipscalereview.com 

ADVERTISING PRODUCTION 

INQUIRIES 

Kim Newman 


b 408.996.7016 > 408.996.7871 

csradv@aol.com 

REPRINTS 

Kim Newman b 408.996.7016 

8 csradv@aol.com 

ADVISORS 

Mark DiOrio MTBSolutions 

Dr. Tom Di Stefano Centipede Systems 

Charles R. Harper Technology Seminars Inc. 

Mark Murdza Antares Advanced Test Technologies 

Dr. Guna Selvaduray San Jose State University 

Dr. Thorsten Teutsch Pac Tech 

Dr. Dietrich Tönnies SUSS MicroTec AG 

Dr. David Tuckerman Tessera Technologies 

Professor C.P. Wong Georgia Tech 

Copyright © 2007 by Gene Selven & Associates Inc. 

Chip Scale Review (ISSN 1526-1344) is a registered trademark 

of Gene Selven & Associates Inc. Publishing headquarters are 

located at 7291 Coronado Drive, Suite 8, San Jose, CA 95129. 

All rights reserved. 

Chip Scale Review is published eight times a year. 

Subscriptions in the U.S. are available without charge to 

qualified individuals in the electronics industry. Subscriptions 

outside the U.S. (eight issues) by airmail are $60 per year to 

Canada or $60 to other countries. In the U.S., subscriptions 

by first class mail are $40 per year. 

PUBLISHER’S LETTER 

We’re Counting Our ABCs for You! 

By Gene Selven, Publisher [gselven@aol.com] 

As part of our continuing commitment to our advertisers and to our readers, 

we recently signed an agreement with the Audit Bureau of Circulations to 

audit the distribution of Chip Scale Review. 

Our advertisers and their agencies use ABC reports and analyses as the basis for 

media buying decisions. Publishers use ABC-audited data to manage circulation and 

develop marketing strategies. 

We have been audited by another auditing agency for the past five years, and we did 

not make this change lightly. We believe, however, that ABC will provide our advertisers 

with a more complete and more accurate picture of our readers and subscribers. 

This is important to our advertisers, of course, because their sponsorship enables us 

to produce and mail the publication to our domestic readership gratis. 

We are, unlike our chief competitor, a completely independent publisher. Our business 

consists solely of Chip Scale Review in English and Chinese; a web newsletter and our 

International Wafer-Level Packaging Conference, which is jointly presented with the SMTA. 

We are also the leading publication in terms of both advertising revenue and editorial 

pages. We have worked hard to achieve this position—one which we’ve held for the last 

four years—and we aim to stay on top! 

Everyone will have total access to our semi-annual circulation audits. They will be 

posted on our web site at www.chipscalereview.com, and we invite you to visit anytime 

to see for yourself. Our first ABC audit will be available in June. 

By the way, I want to assure you that we will continue to guard your privacy. When 

the audit information is gathered, individual subscriber names are never released nor 

sold to any company without an individual’s prior explicit permission. 

China Bound 

As the March issue goes to press, I am preparing for my fourth annual trip to SEMICON 

China in Shanghai. 

To serve the booming China market, we publish two issues in Chinese each year. The 

first is for SEMICON China in March; the second is distributed at NEPCON South China, 

Shenzhen, in August. This year we will distribute nearly 10,000 copies in Shanghai. 

Over the past four-plus years, I’ve witnessed China’s amazing growth personally and 

have spoken to many of the individuals and companies responsible for it. 

We’re now in the early stages of preparing our NEPCON South China issue for distribution 

in Shenzhen. 

Please contact me or one of our representatives about placing your ad in this issue. 

If you’re planning to sell in China, you must make your name, company and products 

known—preferably in the Mainland’s own language. i 


ASSEMBLY LINES 

Farewell to Two Remarkable Leaders 

By Ron Iscoff, Editor [chipscale@gmail.com] 

The man who pioneered the disk 

drive and went on to create an 

industry has died. 

The man who built the world’s largest 

supplier of semiconductor assembly and 

packaging equipment has retired. 

Alan F. “Al” Shugart, author, entrepreneur, 

engineer, salesman, aficionado of 

eye-catching Hawaiian shirts, and 

founder of disk-drive makers Shugart 

Associates and Seagate Technology, died 

in December at age 76 in Monterey, Calif. 

His death was the result of complications 

from heart surgery, according to 

the New York Times. 

Over the past three decades, I met 

with Al about a dozen times in my role 

as a trade journalist. 

The last time I saw him was more 

than a decade ago at a San Jose conference, 

DISKON, an event for disk drive 

industry people. 

He was the keynoter, and while I 

don’t recall the subject of his talk, it was 

controversial and spiced with his 

unique wit. He mentioned in his talk, 

that he didn’t care very much for 

lawyers. He also said that excluded his 

daughter, Teri, who is a lawyer. 

Al was a native of Chino, Calif., and he 

studied engineering at the University of 

the Redlands, where he earned a bachelor’s 

degree in engineering physics. The 

day after he graduated, he went to work 

for IBM as a field service engineer. 

In 1955, while at the IBM Research 

Labs in San Jose, he led the team that 

developed the first hard disk drive, 

RAMAC (Random Access Method 

of Accounting and Control). 

He was also a political curmudgeon, 

who often had little 

patience with the dirty deeds of 

most politicos. In 1996, he 

attempted to place his dog, 

Ernest, on the ballot for congressman. 

He recounts this episode in 

his book, Ernest Goes to 

Washington. 

He’s also the author of 

Fandango: The Story of Two Guys 

Who Wanted to own a Restaurant, 

(which Al did), and The Wit and 

Wisdom of Al Shugart. 

In 1998, he left Seagate, which 

he had formed into the world’s 

largest independent maker of disk 

drives, to found Al Shugart 

International, a resource center to 

help budding entrepreneurs transform 

“great ideas into great companies with 

lasting value,” according to his web site 

[alshugart.com]. 

The Story of ASM 

I have kept the Wiley-Asia book, 

Soaring Like Eagles in a coveted spot in 

my bookcase for about a year, since I 

received a review copy. Now that spring 

cleaning is here, the book has surfaced 

again and begs for comment. 

The authors are Patrick Lam, founder of 

ASM Pacific Technology, and Dr. Edmund 

Lam, who is Patrick’s son and a professor 

of electrical and electronic engineering 

at the University of Hong Kong. 

Al Shugart, the king of Hawaiian shirts. (Courtesy Chris Shugart) 

Although I suspect its publication 

was subsidized by the elder Lam, it’s a 

book worthy of discussion. As the book 

points out, ASM has maintained profitable 

growth for more than 30 years. 

Not everyone can say that! 

The book is subtitled, “ASM’s High- 

Tech Journey in Asia,” and within its 

modestly sized 250 pages, the Lams 

detail their journey from 1975—the 

founding—through 2005, when the 

book was printed. 

If you’re aligned with the equipment 

industry—semiconductor or otherwise— 

it’s likely you will learn a thing or two 

in this slender tome’s pages. 

Continued on page 63 >> 


STANDARDS 

Package-on-Package Is Ready to Take-off 

By Mark Bird, Contributing Editor 

The Package-on-Package (PoP) 

family is one of the fastest 

growing formats in the market. 

In 2005, PoPs accounted for unit volumes 

of 100 million. Last year, that 

unit volume nearly doubled to 180+ 

million and is expected to soar to 

around 700 million by 2010. 

The need for the PoP is to provide a 

cost-effective format for logic and 

memory stacking in the industry to 

address technical, business and logistic 

requirements. 

Dynamic Growth 

The industry has witnessed a range of 

new development programs and a mixture 

of non-standard solutions for PoPs 

over the past few years. The adoption of 

PoPs in 2004 greatly advanced mobile 

phone applications. In addition, the 

development of the JEDEC industry 

standards have stimulated rapid PoP 

growth in volume, growth in applications 

and in the infrastructure. This 

dynamic growth has been experienced 

since early 2005. 

The PoP market is ready for take-off. 

JEDEC JC-63, the Stacked Package 

Product Committee has standardized 

the pinouts and functionality. The package 

registration outlines for the bottom 

and top packages have been addressed 

by the JC-11 Packaging Committee. 

A design-guide standard has also 

been created to address future configurations. 

This standardization coordination 

between the JEDEC committees 

allows the end-customer the flexibility 

to buy the lower, upper and stacked 

combination from a variety of different 

suppliers, giving the end-customer the 

ability to take advantage of high volumes 

at the lowest possible assembly and 

packaging costs. 

The three JC-11 outline registrations 

and design guide are: 

• Lower PoP Package; Very Thin Profile; 

Fine Pitch; Square; 

• Stackable Ball Grid 0.50mm Ball Pitch 

Array Family-MO-266 

• Upper PoP Package; Low Profile, Thin 

Profile and Very Thin Profile; Fine 

Pitch; Square; 0.65 and 0.50mm Ball 

Pitch Array Family-MO-273. 

Future Configurations 

The Lower and Upper PoP Design Guide 

was established to set the stage for 

future configurations. The Design 

Guide is 4.22, Issue A and was published 

in November 2005. 

PoP with single bottom die 

PoP with stacked bottom die 

The latest package registration 

revision is available at www.jedec.org 

in PDF format for downloading at 

no charge. 

All three PoP standards will undergo 

revisions to add 0.80mm ball pitch for 

the upper packages, as well as 0.40mm 

ball pitch for the lower package. This 

The industry has witnessed a range of new development programs and 

a mixture of non-standard solutions for PoPs over the past few years. 

would mean additional variations to the 

registration outlines, as well as an update 

to the Lower and Upper PoP Design 

Guide. The projected time of this activity 

will be late this year. i 

Mr. Bird is a Technology Fellow and the 

COO at Mbird and Associates Semiconductor 

Assembly, Packaging and Standardization 

Consultants in Apache Junction, Ariz. He 

is also the chairman of the JC-11 Packaging 

Standards Committee and technical 

advisor/chief delegate for the United States 

to the IEC TC47 and SC47D Semiconductor 

Committees. [j_mark_bird@yahoo.com] 

8 

Chip Scale Review ■ March 2007 ■ [ChipScaleReview.com]

plasma cleaning solutions 

With productivity 150% of conventional 

models and patented parallel plate 

technology that delivers superior 

results for both etching and 

surface modification, interest in 

Panasonic’s plasma solution 

continues to skyrocket. 

Experience industry-leading 

mold resin adhesion and under-fill 

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It’s brilliant. 

PSX303

TEST PATTERNS 

The ‘Mainframe Mentality’ Lives On! 

By Paul M. Sakamoto, Contributing Editor–Test [paul.sakamoto@inovys.com] 

I 

would guess that about half of 

you who read this column 

remember the time when mainframe 

computers roamed the land. 

The closely related mini-computer 

was its scaled-down little brother. Aside 

from the fact that they were very large 

by today’s standards, these machines all 

had proprietary operating systems and 

programming languages. 

This required specialized training for 

the various models from different manufacturers. 

Additionally, the networking 

between these machines was very difficult 

and aided the growth of specialized 

companies to address the task. 

Slow to Adopt Standards 

The biggest reason that the industry was 

slow to adopt standards was that it 

allowed vendors to keep their customers 

virtually enslaved once users adopted a 

maker’s proprietary system. 

It also allowed the manufacturer to 

charge for a very wide variety of related 

goods and services that only they could 

provide. 

Fortunately, today we have standards 

for software, applications and networking 

that are applied very broadly. These 

standards allow the direct re-use of data 

and information on virtually all current 

computers, smart phones, PDAs, and 

other computing machines. 

My rant today is that this is not the 

case for ATE. 

3600Plus & 3700Plus 

More performance with 

fewer limitations. 

The 3600Plus and 3700Plus wire bonders break new ground 

in innovation and design. Offering you more performance, 

options and versatility, the Plus Series combines intuitive 

technology with quality and reliability: 

• PowerRibbon TM Option for ribbon sizes 20 mil x 4 mil to 

80 mil x 8 mil 

• Bond Process Monitoring (BPM) flags suspect bonds in 

real-time, stores process information for later evaluation 

• Active Loop Control (ALC) bondheads allow best-in-class 

loop control and non-destructive pulltesting 

• Offline Programming Tool (OPT) converts CAD files into 

machine process programs, maximizing machine uptime 

New machine capabilities for greater performance, new 

international offices for better service, and a new interconnect technology 

— Orthodyne is committed to giving customers more. 

10 


Now, some of you may say, “Hey, 

Paul, you’re wrong. Company ABC 

adheres to the IEEE x standard.” 

This is likely true, but it is completely 

not the point. One could also say, 

“What about the Semiconductor Test 

Consortium/Open Architecture 

Initiative?” It’s a decent shot, but so 

far is more widely talked about than 

widely used. What I am talking about is 

the ability to develop a program on a 

tester from one company and run it on 

a standards-compliant tester from 

another company without any new 

programming. 

This just doesn’t happen today. The 

programming languages for each tester 

are different enough to require a conversion 

process for all program porting. 

This is a time-consuming and expensive 

process in most cases. It can also be 

error-prone, which is the most expensive 

problem of all. 

Mainframe Mentality 

The main reason that ATE companies 

promulgate the proprietary model— 

while sending delegates to standards 

meetings—is that they still have the old 

mainframe mentality. 

These manufacturers hope to protect 

their domains by making sure their customers 

are enslaved by their sunk cost 

in training, programs, infrastructure 

and other legacy ballast. The customers 

become enslaved by their own expertise 

with these systems. 

The cost of this model is high to all 

parties. The ATE companies miss the 

leverage of having the common issues 

be common. That is, they spend a lot of 

time working out the details of their 

Mainframe computers have come along way over 

the years. This is a photo of the original ENIAC 

computer that occupied a football-sized room. 

(U.S. Army photo) 

proprietary language and architecture 

instead of spending those resources on 

market differentiation and added value. 


Patent Pending 

PowerRibbon 

More power with 

fewer connections. 

For years, Orthodyne’s ultrasonic small and large wire bonders have led the 

market in innovation and efficient, reliable performance. Our new 

PowerRibbon technology extends that tradition as it creates a new 

category of interconnect for power devices. 

Sized 20 x 4 mil to 80 x8mil,PowerRibbonoffers the solution to smaller 

packaging – more power with fewer connections. PowerRibbon combines 

the flexibility and robustness of large aluminum wire bonding 

with greater current-carrying capacity and lower RDS ON . Efficient, reliable 

and retrofittable, PowerRibbon is the most advanced interconnect 

alternative for small SO8, PQFN type leadframe applications as well 

as complex power modules. 

To find out more about PowerRibbon or the Plus Series 

bonders, contact us. 

16700 Red Hill Avenue 

Irvine, CA 92606-4802 

Phone: +1-949-660-0440 

sales@orthodyne.com 

www.orthodyne.com 

Orthodyne Electronics GmbH 

Lina-Ammon-Strasse 15 

90471 Nuernberg, Germany 

Ph: +49-(0)911-98813-0 

Fax: +49-(0)911-98813-20 

Laerchenster. 2 

83533 Edling, Germany 

Ph: +49-8071-93215 

Fax: +49-8071-93217 


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INDUSTRY NEWS 

APEX 2007 Los Angeles: A Report from Smogville 

By Ron Iscoff, Editor 

The IPC’s APEX show, 

which trimmed the sails 

from the venerable 

and—until 2000— 

unchallenged NEPCON 

West behemoth seven 

years ago, has transformed 

itself into a 

regional printed circuit 

board show. 

This is not surprising, 

since it’s co-located with 

the same trade group’s 

Printed Circuits Expo. 

Regional Show 

Certainly, there is nothing wrong 

with a regional printed circuits 

show, but there’s also not much to 

Teraflop Computer Shrinks to Fingernail-Sized Processor 

Santa Clara, Calif.—Intel 

Corporation researchers 

have developed the world’s 

first programmable processor 

that delivers supercomputer-like 

performance from 

a single 80-core chip not 

much larger than the size of 

a fingernail. The processor 

uses less electricity than most 

of today’s home appliances— 

just 62 watts. 

The “Tera-scale computing” 

research is aimed at delivering 

teraflop—or trillions of calculations 

per second—performance. 

Technical details of the teraflop 

research chip were presented in 

February at the annual International 

Solid State Circuits Conference in 

San Francisco. 

The teraflop chip also features a 

mesh-like “network-on-a-chip” 

It’s 50 years for IPC and the fourth location for APEX this 

year. Visitors benefitted from generally excellent weather and 

a revitalized downtown Los Angeles. (Chip Scale Review) 

see for chip devotees, unless they’re 

also making printed circuit boards. 

And there’s no reason, really, to 


This board houses Intel’s 80-core teraflops research 

chip. The board contains working silicon and is the 

world’s first programmable chip to achieve teraflops 

performance while consuming very little power. (Intel) 

architecture that enables super-high 

bandwidth communications 

between the cores, and is capable of 

moving terabits of data per second 

inside the chip. 

Intel has no plans to bring this 

exact chip designed with floating 

point cores to market. 


IBM and Intel Claiming 

45nm Transistor Honors 

Intel President Paul Ottolini holds an Intel Core 2 Duo 

microprocessor. (Intel Corp.) 

San Jose—In announcements released 

nearly simultaneously, giants IBM and 

Intel are both claiming next-generation 45 

nanometer transistor honors employing 

separate processes with apparently similar 

materials. 

Intel, Santa Clara, calls its technology, 

“The biggest change to computer chips in 

40 years” and “one of the biggest advancements 

in fundamental transistor design.” 

IBM, Yorktown Height, N.Y., terms its work 

“The first fundamental change to the basic 

transistor in 40 years.” Neither company 

names the other in their news releases. 


A New Interconnection Technology 

Blooms at Jerry Falwell’s University 

Los Angeles—What do the Rev. Jerry 

Falwell and Liberty University, the fundamentalist 

Baptist institution he founded, 

have in common with the semiconductor 

industry? 

Until recently, the answer would have 

been nothing. 


INSIDE NEWS 

• Worldwide Silicon Shipments Rise by 20 

Percent page 64 


14 


INDUSTRY NEWS 

APEX Continued from page 13 >> 

exhibit unless you’re selling to the folks 

who make, sell or buy PWBs. 

As I made my rounds, the comments 

were mixed, but generally favorable 

about the show. Most of the people I 

spoke to thought the show was much 

smaller this year. 

Not so! said Anna Garrido, the IPC’s 

marketing and communications lady, 

when I questioned her in the press room. 

During the three-day run of exhibits, 

floor traffic was modest on Tuesday and 

Wednesday and slowed to a trickle on 

the third and final day. It would not be a 

challenge for most people to cover all 

exhibits in one day. 

According to a 2006 IPC news release, 

some 14,967 square meters (161,000 square 

feet) of the Convention Center were expected 

to be occupied by exhibitors. Attendance 

figures were not were not forthcoming by 

our deadline, two weeks after the show. 

In fact, she reported, this year’s APEX 

boasted more exhibitors and more overall 

exhibit space than the prior year. It 

didn’t seem like it to me or almost 

everyone else I talked to. Perhaps it was 

the lack of skyscraper exhibits which 

Booth arrangements presented a clear “line-ofsight” 

from one end of the hall to the other. 

we’ve come to expect, with their cantilevered 

rooftops and meeting rooms 

on second or third levels. 

Could the problem be the location— 

The Los Angeles Convention Center that 

dominates two massive city blocks in 

downtown Smogville. 

Fourth Location 

This was the fourth location for APEX 

since its first show in 2000. The Printed 

Circuits Expo, which was initially a separate 

event, was joined at the shoulder 

to APEX in 2004. In 2000, NEPCON 

West ran a bifurcated show in Anaheim, 

about two weeks before APEX. And then 

NEPCON West ran out of steam as the 

IPC cut NEPCON’s excessive exhibiting 

prices by half. 


Intel Continued from page 13 >> 

However, the research is instrumental in 

investigating new innovations in individual 

or specialized processor or core 

functions, the types of chip-to-chip and 

chip-to-computer interconnects required, 

and—most importantly—how software 

will need to be designed to leverage 

multiple processor cores most efficiently. 

Power Cores On/Off 

The research also investigated methods 

to power cores on and off independently, 

so only the ones needed to complete a 

task are used, providing more energy 

efficiency. 

Further research will focus on the 

addition of 3-D stacked memory to the 

chip. The Tera-scale program has over 

100 projects. 

ASCI Red, the first computer to benchmark at a 

Teraflops in 1996, used nearly 10,000 Pentium 

Pro CPUs. 

Teraflop performance was first 

achieved in 1996, on the ASCI Red 

Supercomputer built by Intel for Sandia 

National Laboratory. 

That computer occupied more than 

186 square meters, was powered by nearly 

10,000 Pentium Pro processors, and 

consumed over 500kW. [intel.com] ■ 


INDUSTRY NEWS 

APEX 2007 PHOTO ALBUM 

The APEX conference, co-located with IPC’s 

Tuesday – Thursday FEBR 

Printed Circuits Expo and Designers Summit, 

Los Angeles Convention Cente ® 

enjoyed mostly sunny skies for its first year in Los 

® 

FOR MORE INFORMATION Angeles. Next year, the event is scheduled to return 

and the DESIGNERS SUMMIT 

contact 877-472-4724 (US/Can to the Los Angeles Convention Center from 

February 17-21, with exhibits running from February 19-21. (See the editor's 

report beginning on page 13.) 

Show visitors included Jerry Cohen, president of 

Pure Technologies, Atlanta, and his First Lady, 

Marsha Cohen. 

Dage, a maker of bond testers and x-ray inspection 

equipment, had a new owner, Nordson, at this 

year’s APEX. 

Finetech’s Adrienne Gerard and Neil O’Brien discussed 

direct component printing with show visitors. 

Gene Selven, Chip Scale Review publisher, 

stopped to chat with Heraeus’ Christina Kistler. 

16 


INDUSTRY NEWS 

As usual, Panasonic’s exhibit was a dazzler—big, bold and brassy! 

Henkel’s Doug Dixon and Elaine Yee talk 

about the company’s new products. 

George Tint of HDI Solutions, Santa Clara, demonstrates 

the HIOKI Hi-Tester. 

Ron Levinson (left), Chip Scale Review representative, 

stops by to chat with Alec Moffat of Machine 

Vision Products. 

Don Miller, president of YESTech, San Clemente, 

Calif., demonstrates a new product. 

Paul Niemczura, Heraeus’ manager of 

technology development, makes a point. 

The Indium booth once again gets our vote for the most 

esthetically pleasing exhibit at APEX. 


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INDUSTRY NEWS 

IBM and Intel Continued from page 13 >> 

High-k + Metal Gate Transistors 

Metal Gate 

• Increases the gate field effect 

High-k Dielectric 

• Increases the gate field effect 

• Allows use of thicker dielectric 

layer to reduce gate leakage 

HK + MG Combined 

• Drive current increased >20% 

(>20% higher performance) 

• Or source-drain leakage 

reduced >5x 

• Gate oxide leakage reduced >10x 

S 

HK+MG 

Transistor 

Silicon Substrate 

Low resistance layer 

Metal gate 

Different for NMOS and PMOS 

High-k gate oxide 

Hafnium based 

D 

combined: The problems are Fermilevel 

pinning and “phonon scattering.” 

Joint Development 

IBM’s work has been conducted jointly 

with Sony, Toshiba and Intel’s arch 

nemisis AMD. 

IBM says it has already “inserted” the 

technology into its East Fishkill, N.Y., 

fab and will begin to produce ICs at 

45nm beginning next year. 

This technology, termed “high-k 

metal gate,” substitutes a material in 

place of Si, although the material type 

was not disclosed. [ibm.com] 

[intel.com] ■ 

This graphic, based on Intel-supplied information, 

illustrates the company’s 45nm High-k + metal 

gate transistor. 

Next-Generation CPUs 

Intel says the process will be employed 

in its next-generation of Core 2 CPUs— 

already in house—the first of at least 15 

45nm processor products in development 

at the company. 

The development, Intel adds, will 

enable “record speeds,” while reducing 

electrical leakage that can adversely 

affect power consumption, noise and 

costs. 

It will also ensure that Moore’s Law 

“will thrive well into the next decade,” 

the microprocessor leader claims. 

Intel says it is using a new material 

combination of high-k gate dielectrics 

and metal gates. The company will begin 

production of the first 45nm CPU 

(Penryn) in the second half of this year. 

Intel Beating the Competition 

Its development is more than a year 

ahead of its competitors, Intel claims. 

In its 45nm technology, Intel has 

employed a hafnium-based, high-k 

material in the gate dielectric. The 

dielectric is created with atomic layer 

deposition (ALD), where a single layer 

of the high-k material molecule is 

deposited at a time. 

Because the high-k gate dielectric is 

not compatible with current Si gate 

electrodes, Intel said it had to develop 

the new metal gate materials to solve two 

problems that arise when the two are 

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INDUSTRY NEWS 

Taiwan Will Be the Largest 

Equipment Market in 2007 

Washington, D.C.—Taiwan will be the 

biggest spender for chip-making equipment 

in 2007, according to a report 

published by the U.S.-Taiwan Business 

Council. 

Semiconductor Report–Annual Review 

2006 says that 2006 was an exceptionally 

strong growth year for Taiwan’s leading 

foundry and DRAM chipmakers, and 

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in 300mm wafer fabs and the establishment 

of new partnerships, Taiwan is 

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Taiwan is poised for a record year. 

CALENDAR 

APRIL 

10-12 IPC/JEDEC Global Conference 

on Lead-Free Reliability and 

Reliability Testing for RoHS Lead- 

Free Electronics, Boston, Mass. 

[ipc.org] 

24-26 SMT/Hybrid/Packaging 2007, 

Nuremberg, Germany 

[smt-exhibition.com] 

MAY 

8-10 SEMICON Singapore, 

Singapore [semi.org] 

May 29-June 1 ECTC 2007: 57th 

Electronics Components and 

Technology Conference, Reno, Nev. 

[ectc.net] 

JUNE 

4-6 IEEE 2007 International 

Interconnect Technology Conference, 

Burlingame, Calif. [ieee.org] 

13-15 PEAKS Symposium on 

Advanced Cleaning Technology, 

Whitefish, Mont. [semitool.com/peaks] 

JULY 

SEMICON West 

16-20 (Conference), 17-19 (Exhibits), 

Moscone Center, San Francisco 

[semi.org] 

Simtek Corp. Hires Hulse for Worldwide Marketing Post 

Colorado Springs, Colo.—Grant Hulse 

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nonvolatile SRAMs, as vice president of 

worldwide marketing. He joined the 

company from Qualcomm, where he 

was an RF product line manager. 

Hulse reports to Simtek president 

Harold Blomquist, and will be based in 

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INDUSTRY NEWS 

SEMICONDUCTORS AND THE LAW 

TI Did Not Infringe Patent for DSPs, U.S. District Court Rules 

Dallas—Texas Instruments did not 

infringe a digital signal processor patent, 

according to a ruling by the U.S. District 

Court for the Central District of California. 

The Court granted a summary judgment 

for TI in ruling against a suit brought 

Micro-volume dispensing requires three core 

technologies. Without them, you can forget 

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by Microprocessor Enhancement 

Corp. (MEC), a subsidiary of Acacia 

Research Corp., Newport Beach, Calif. 

MEC was seeking more than $94 million 

and a permanent injunction 

against TI’s C6000 DSP platform. The 

THERE ARE NO SHORTCUTS 

TO A 5-MIL DOT 

Court also ordered MEC to pay TI’s 

court costs. 

MEC filed suit against both Intel 

Corp. and TI in April 2005, alleging 

patent infringement by Intel’s Itanium 

microprocessors and certain DSPs sold 

by TI. The Intel litigation is still pending. 

The MEC patents relate to an architecture 

employed in advanced pipeline 

processors. This architecture enables 

conditional execution of processor 

instructions and a whether the instructions 

should be written back to memory. 

By conditionally executing instructions, 

according to MEC, the processors gain 

significant improvements in speed. 

[acaciaresearch.com] [ti.com] 

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Dr. Mackie Joins Indium 

As Semi Product Manager 

Clinton, N.Y.—Dr. 

Andy Mackie has 

joined the Indium 

Corp. of America as 

product manager for 

semiconductor 

packaging materials, 

based at the company’s 

Dr. Andy Mackie Clinton headquarters. 

Dr. Mackie brings 

more than 17 years of experience in new 

product development, sales, and marketing 

of electronics assembly and semiconductor 

packaging to the company. 

He received the IPC President’s 

Award in 2001 for his leadership in 

IPC’s Solder Paste Task Force and the 

Assembly and Joining Materials 

Subcommittee. 

He holds a Ph. D. in physical chemistry 

from the University of Nottingham, 

England, and a master’s degree in surface 

and colloid chemistry from the University 

of Bristol, England. [indium.com] 

www.chipscalereview.com 

22 


INDUSTRY NEWS 

Packaging Industry Veteran Opens Technical Sales Firm 

From left, Augustine Yap, Cristel Technologies; Takehiko Murakami, Minami; Yoshihiro Shimada of PacVision 

Corp., Japanese rep for Minami and PTA; Danny Fields; S.Y. Lee and Celina See, both of PTA. 

San Jose—Danny Fields, a 20-year 

veteran of the semiconductor packaging 

industry, has founded Pacific Gate 

Technologies, a technical sales firm. 

For nearly a decade, Fields was sales 

director for IPAC/i2a, San Jose, a 

provider of advanced semiconductor 

packaging and test. 

He earlier held similar titles and posts 

at AIS and AME/IMI, semiconductor 

assembly vendors offshore. 

Pacific Gate’s initial clients are Minami 

of Fuchu City, Japan [ho-minami.co.jp], 

a maker of screen printing and reflow 

systems for surface mount and device 

packaging; and PTA [polarta.com],a 

provider of IC assembly services based 

in Penang, Malaysia. 

Minami offers a low-cost screen 

printing system for wafer-level CSPs, 

with ball diameters ranging from 95 to 

500 microns. [pacgate-us.com] 

Silicon Nanowire Biochip Will Speed Genetic Tests 

Singapore—A new, highly sensitive 

biochip, based on silicon nanowire technology, 

will revolutionize the detection 

and analysis of RNA and DNA, according 

to its developers. 

The biochip will be produced through 

the combined efforts of Singapore’s 

Institute of Microelectronics (IME), 

Australian-based BioChip Innovations 

and SiMEMS, also of Singapore. 

The biochip, according to the developers, 

will shorten the time for genetic 

testing by directly detecting single DNA 

or RNA molecules. Because of their 

nanometer scale, silicon nanowires 

enable a greater sensitivity of detection. 

The nanowires can also detect biomarkers 

and other bio-molecules such 

as bacterial, viral and other specific 

genetic sequences. 

Uppili Raghavan, SiMEMS CEO, says 

most biochip systems now in use or 

IME is developing a nanowire biochip in a joint program 

with an Australian and Singaporean company. 

under development employ complex 

and expensive optics, signal processing 

systems and data interpretation, “all of 

which are impediments to adoption by 

the diagnostics industry.” 

The nanowire devices can be manufactured 

in standard CMOS silicon 

foundries, allowing them to be mass 

produced “reliably and cost-effectively,” 

Raghavan says. 


INDUSTRY NEWS 

Mirrored Pinouts Continued from page 13 >> 

Invention Donated 

However, last year inventor Charles S. 

Clark, the father of two Liberty University 

alumni, and a 30-year veteran of the electronics 

industry, donated his invention 

for “mirrored pinouts” to the university. 

Martin “Marty” 

Hart, meanwhile, is 

a veteran of the 

semiconductor 

industry and the 

“King of Dummy 

Components,” which 

he has purveyed for 

Martin Hart several decades 

through his Garden 

Grove, Calif., company, TopLine 

[topline.tv] 

Liberty, with no experience in semiconductors 

or electronics, decided it 

needed a way to bring Clark’s invention 

to market. The university took a booth 

at last year’s PCB West, hoping 

to interest someone with experience 

and connections. 

Hart was drawn to the 

Liberty booth at the show and 

discussed the invention with 

Clark, he told Chip Scale Review 

recently at APEX in Los 

Angeles. When Clark explained 

it, says Hart, “I realized that my 

life would not be the same again.” 

Letter of Intent Signed 

As a result of the meeting, 

Liberty has signed a letter of intent with 

Hart to take the mirrored pinout from 

concept to production. Liberty has also 

filed a patent for the invention and 

believes it may be worth “many, many 

millions of dollars.” Hart agrees. 

The benefits of the mirrored pinouts 

are a smaller circuit board, a faster circuit 

speed, reduction of inner layers (for 

U1 

Standard 

Pinout Pin 1 

Pin 1 

A 

B 

A ~ B = 20mm 

U1=Standard Pinout 

U2=Mirrored Pinout 

Mount same side of board. 

U2 

Mirrored 

Pinout 

This graphic shows the very short routing, 20mm in this case, 

between a standard pinout and a mirrored pinout on a board. 

reduced EMI), and lower cost. With a 

standard pinout, the circuit routing is 

relatively long. By combining standard 

pinout ICs together with mirrored 

pinout devices, however, the routing 

distance is very short, as shown in the 

illustration. 

The project has been taken over by 


24 


INDUSTRY NEWS 

Mirrored Pinouts Continued from page 24 >> 

Hart’s startup, Mirror Semiconductor 

[mirrorsemi.com]. He’s in the very early 

stages of proof of concept, and is talking 

to prototype shops like Corwil. He 

believes as many as 20 percent of the 

boards currently built may ultimately 

have a small percentage of devices with 

mirrored pinouts on them. 

Most of the same IC assembly equipment 

used traditionally will be 

employed for the mirrored pinouts 

(MPs), except that MP packages are 

wirebonded in a clockwise direction, 

while standard pinouts are wirebonded 

in a counter-clockwise direction. Hart 

says he’s also considering deploying 

Microbond’s “Xwire” for bonding. 

New Software 

The greatest change in the IC device 

assembly process, he says, will involve 

designing new wire bonding software, 

and special fixtures will also be needed. 

“If the market will embrace MPs,” he 

adds, “we’re looking at capturing six billion 

devices that are now being packaged 

per year, which is only 5 percent of the 

total number of packages.” 

Part of the anticipated business, says 

Hart, will be as a fabless IC maker, 

delivering IC devices using the MPs. 

The other part of Mirror Semi’s revenue, 

he adds, will come from customers 

who want to license the technology, 

such as packaging foundries, OEMs, 

ODMs and other fabless IC makers. 

Essentially, any semiconductor can be 

made into a package with a mirrored 

pinout, and the MPs, known by the 

trademark “MirrorChips,” can be mixed 

on the same board with standard pinouts. 

Based in Irvine, Calif. 

The startup will be based in Irvine, 

Calif., near but separate from TopLine’s 

Southern California home. Hart says he 

has already lined-up representative 

offices in France, Germany, Japan, 

Korea, Sweden and the U.S. 

“We are now looking for both strategic 

partners and venture capitalists,” 

Hart says. If the MP is the success he 

believes it will be, Hart plans to “pick a 

successor for TopLine.” 

While he believes the first key application 

may be for parallel data bus circuits, 

the MP could have extensive 

applications for many devices, including 

microcontrollers, memory ICs and digital 

signal processors. ■ –Ron Iscoff, Editor 

‘Big 10’ OEMs Accounted for $84 Billion of Chips Consumed 

Stamford, Conn.—The top 10 OEMs 

accounted for $84 billion of the semiconductor 

market in 2006. This figure 

represents one-third of all semiconductors 

consumed, according to industry 

analyst Gartner Inc. 

This figure represents a 9 percent 

increase from 2005, when the top 10 

OEMs accounted for $77 billion of 

semiconductor sales. 

HP was the biggest chip consumer 

with about $12 billion, but Nokia and 

Dell closed to within $0.5 billion. 

Samsung and Sony completed the top 

five, followed by Motorola, Siemens, 

Toshiba, LG and Apple Computer. 

According to Alfonso Velosa, 

Top 10 OEM Semiconductor Consumption, 

2005-2006 (Billions of Dollars) 

Company 2006 2005 

HP $12 $12 

Nokia $12 $10 

Dell $12 $11 

Samsung $9 $8 

Sony $9 $9 

Motorola $8 $7 

Siemens $8 $7 

Toshiba $5 $5 

LG $4 $4 

Apple $4 $4 

(Source: Gartner Dataquest, Jan. 2007) 

Gartner’s research director, “Data processing 

and telecommunications firms 

represented 75 percent of the total 

semiconductor spending by the top 

consumers.” [gartner.com] 


INDUSTRY NEWS 

APEX Continued from page 15 >> 

Here’s a recap of locations and dates, 

in case you are now keeping score: 

Year Location Date (Exhibits) 

2000 Long Beach March 12-16 

2001 San Diego January 16-18 

2002 San Diego January 22-24 

2003 Anaheim March 31-April 2 

2004 Anaheim February 24-26 

2005 Anaheim February 24-26 

2007 Los Angeles February 20-22 

2008 Los Angeles February 19-21 

We think the hallmark of a good 

event is to keep a similar date and location. 

After every change in venue, there 

is a learning curve for the sponsor, for 

the exhibitors and for the visitors. 

The only venue that APEX has booked 

long enough to overcome that curve was in 

Anaheim. Now we’ve begun climbing up 

the learning curve again. Yes, we realize 

that the Anaheim Convention Center 

told the IPC not to return because the 

show didn’t bring in enough money. 

A Fizzler 

As it turned out, Intel Corp. took over the 

Anaheim dates for an event that reportedly 

fizzled. 

After stumbling around dates for five 

years, finally, in 2005 it appeared IPC had 

finally locked into mid-February. Now if 

they can only keep the same location! 

The rarely lamented NEPCON West 

show kept virtually the same dates 

(beginning of March) and same location 

(Anaheim Convention Center) for nearly 

all of its 30 plus years. 

That said, the Los Angeles Convention 

Center didn’t turn out to be as bad a choice 

as we expected. Downtown L.A. has 

undergone a renaissance over the past 

few years and the Convention Center is 

a major beneficiary of gentrification. 

Wandering Around 

We complained loudly about the lack of 

proper signage directing us to the show. 

Although the IPC shows only used one 

large hall, the LACC has four of them, with 

directional names. We were wandering 

around West Hall (visions of SEMICON 

West!) for 10 minutes before realizing the 

show was in South Hall (or was it North Hall)! 

My pal, Joe Marcello, a retired veteran 

of the semiconductor packaging industry 

and attendee/speaker/exhibitor at 

zillions of trade shows in almost every 

niche of the world, barked to me, 

“They’d never get away with this lack of 

signage in Europe, Ron!” 

Keynoter astronaut Buzz Aldrin describes his 

space flight while IPC captures the moments on 

video. Joseph Fjelstad is at Dr. Aldrin’s left. 

In fact, poor signage, while it seems a 

simple matter that I have already spent 

too many words on, has been one of the 

chief complaints at SEMICON West 

every year! It’s typically these little 

annoyances that people remember. 

In addition to exhibits, of course, were 

the technical papers and the keynotes. 

The celebrity speaker was astronaut Dr. 

“Buzz” Aldrin. 

We understand it costs about $30,000 

to hire Buzz as your speaker. Perhaps the 

IPC could have spent a few of those dollars 

on signage and gotten someone 

closer to the electronics industry as the 

keynote for a few dollars less, or free. ■ 

F&K Delvotec North America, 27182 Burbank 

Foothill Ranch, CA 92610, phone 949/595-2200, fax 949/595-2207 

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Are Wire Bonders Running Out of Steam? How this 

Essential IC Assembly Tool Is Keeping Pace 

Unlike this venerable old steam-driven train, wire bonders have undergone constant improvement over the past 50 years. 

Wire bonders are becoming smarter, faster and more cost-effective on 

the assembly line. In the bonder’s 50+ year history, the machines have 

become not only the icon for IC assembly, but the most-needed tool at 

every IC assembler. Is there room for improvement? Of course, and 

we’ll explore that topic in this article. 

By Ron Iscoff, Editor 

[chipscale@gmail.com] 

We are gathered here today 

on this field of honor to 

commemorate, to celebrate and to 

memorialize the outstanding role 

played in the semiconductor assembly 

industry by wire bonders. 

We will long remember (nor soon 

forget) the row upon row of automatic 

wire bonders that were the 

stuff of almost every semiconductor 

assembler from Amkor to STATS 

ChipPAC. 

28 


Even though they have been replaced 

by processes that package our integrated 

circuits at locations several million light 

years from our earth, and at a speed and 

pitch that boggle the mind, the venerable 

wire bonder deserves much credit for 

the early success of the semiconductor 

packaging industry. 

Hey, not so fast! 

If you feel my eulogy is premature, of 

course you’re right! The wire bonder has 

not run out of steam yet; not by a long 

shot! In another two or three decades, 

who knows? But for now, the wire bonder 

is still the king of every IC assembly and 

packaging house from China to Taiwan. 

Remember, American humorist Mark 

Twain (Samuel Clemens) once wrote the 

New York Journal to advise them, “The 

report of my death was an exaggeration.” 

Ditto for wire bonder naysayers! 

About Pitch 

Speeding up wire bonders has never 

been a problem. From the early days of 

manual units, beginning with the 

granddaddy of them all from Kulicke & 

Soffa Industries to contemporary 

production units, 

speed has evolved to meet 

users’ needs. 

The technical issues have 

usually revolved around 

pitch—the distance between 

the center of adjacent pins— 

and then accuracy and 

repeatability, more than 

other issues. And from what 

we continue to see, new technology 

keeps resolving these 

issues, as well. 

Dr. Gerald K. “Skip” Fehr 

has had an ongoing, intimate 

relationship with wire bonders 

for decades at Fairchild, 

IPAC, Intel and LSI Logic, 

among others. 

Now an industry consultant 

in San Jose, Dr. Fehr recalls the old 

manual bonders employed in production, 

which required manual “pig tailing.” 

Over the years, wire bonders have 

become faster and offered better control 

This is F&K Delvotec’s 6600G5 heavy wedge wire bonder, which 

enables package changeover in about 3 minutes. 

Shortfalls 

What are the shortfalls of today’s wire 

bonders? “I think we are really asking 

the machines to do more and more, and 

the issues tend to be related to the 

‘I think we are really asking the machines to do more 

and more, and the issues tend to be related to the 

development time needed to prove out the capability.’ 

Oerlikon’s ESEC branded WB3100optima is a 

thermosonic ball bonder. 

of the ultrasonics. (Dr. Fehr added door 

bell buzzers to the first bonders he 

bought for Intel, cutting the bonding 

time to 0.3 seconds and yielding more 

reliable bonds.) 

Other improvements, he notes, 

include the addition of automatic imaging, 

which at first “had serious issues 

with finding the edge of the pads due to 

light sensitivity.” This automation has 

improved so much that it can easily 

handle 1000+ pad devices. 

Wire bonders have also been asked to 

handle various loops for multi-tier 

devices, multi-pad rows and to bond 

multichip packages. “One of the latest 

demands has been for them to handle 

the weak pad structures of low dielectric 

materials,” Dr. Fehr says. 

development time needed to prove out 

the capability.” 

There are wire-bonder limitations 

where flip-chip offers some major 

advantages, Dr. Fehr observes, “but the 

wire bonders are alive and well, mainly 

because they are a lower-cost alternative 

to other processes.” 

Amkor Technology Inc., Chandler, 

Ariz., one of the largest IC packaging/ 

test foundries in the world, continues to 

engage heavily in joint development 

programs to evaluate next-generation 

wire bonders. 

The latest wire bonders, says William 

Stermer, senior manager of Amkor’s 

wire bond process and BGA business 

unit, says the latest generation of wire 

bonders provide many new features, 


“some of which are promising. 

“Other features,” Stermer 

adds, “although showing 

potential, still have many 

issues to resolve before optimized, 

high-volume manufacturing 

performance can be 

realized.” 

The ultra-high-speed Maxµm plus from Kulicke & Soffa 

Industries is suited to many production applications. 

Admirable Features 

Some of the more admirable 

features, says Stermer, include: 

• Increased bonding UPHs 

made possible by a wire 

cycle time of 60ms for a 

2mm wire length and the 

employment of twin bonding 

heads 

• Overall manufacturing yield 

improvements due to ball 

placement accuracy honed to 2.5µm 

and dual magnification that allows 

bond-pad pitch reductions to 35µm 

F&K Delvotec’s 5610 universal gold ball bonder is also a wire 

bond tester. 

• Improved machine uptime through 

enhanced capillary cleaning and better 

post-bond inspection. 

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30 


There is, however, still room for 

improvement, says Stermer, who offers 

these examples: 

• Ease of work-holder set-up, specifically 

for thin leadframes and substrate 

handling, currently requiring 

many assists and adjustment 

• Drifting balls, inconsistent looping 

The Windows-based operating system is 

“much more user-friendly” compared to 

older versions. Yet, Stermer says the 

software is unstable, and the process 

portability function should be 

enhanced. Additionally, many new 

parameters are offered only within hidden 

screens. 

Curtis Escobar, senior process engineer 

at CORWIL Technology Corp., a Milpitas, 

Calif.-based IC assembler, has some 

thoughts about wire bonders, as well. 

Current fine-pitch capability with 

tight tolerances for bonding force, the 

ultrasonics and placement accuracy are 

particularly helpful, says 

Escobar, for bonding to MEMS, 

low-k, thin-layer- and “fragile 

structure” die. 

Improvement Needed 

Troublesome features with wire 

bonders, says Escobar, include 

mechanical clearance issues, with 

increasingly complex and multilevel 

packages, PWBs, and so forth. 

Also problematic are wire 

supply spooling and feed. 

“When is the fully automatic 

self-wire-threading wire bonder 

coming? Escobar ponders. 

Wire bonding is both an academic 

and practical issue to Dr. 

Herbert Reichl of Fraunhofer 

IZM, Berlin, Germany. 

Worthy of praise, says Prof. 

Reichl, is the strong development 

trend toward user interfaces 

that are intuitive. 

Orthodyne’s 3700 Plus is a dual-head, ultrasonic bonder 

available as a wedge, ribbon or wire unit. 


The Eagle 60AP is ASM Pacific’s entry in the thermosonic 

ball bonder market. 

Additionally, there is a growing integration 

of features that allows the automatic 

programming of repeated wirebond 

structures (many bonds with constant 

pitch). 

This is Orthodyne’s 7200 ultrasonic, twin-head wedge bonder. 

Also, he adds, digital transducer 

systems that are able to 

point-out incorrect configurations 

would be helpful, too. For 

example, a falsely mounted 

transducer will cause a change 

in the impedance curve during 

the transducer test. 

In about five years, predicts 

Dr. Reichl, machines will be 

connected to an external database 

that will make it possible 

to evaluate quality and process 

data via linked PCs. 

Troublesome 

Despite the quality of today’s 

wire bonders, programming of 

complex layouts remains very 

time consuming, despite the 

automation features that have 

already been added to current 

machines, says Dr. Reichl. 

A standardized data format that 

includes key configurations such as 

positions of bond pads, alignment 

marks and wires that can be exported 

from the CAD 

system would 

be appreciated, 

he adds. 

Machines are 

now dependent 

on environmental 

conditions, 

such as 

temperature, he 

says. “The integration 

of 

monitoring 

instruments is 

needed.” 

Today, the 

control of ball 

dimensions is 

difficult (manual 

effort and 

difficult measurement 

of the 

ball shape at 

The Palomar 8000 is a gold ball bumper and bonder. 

the microscope) is the norm, he 

observes. An optical Efficient Fiber 

Optics (EFO) control system at the bonder 

could be a valuable feature and has 

already been mentioned in publications 

by ESEC (Oerliken). 

“However, there are systems that 

measure the deformed ball after bonding 

from a top view,” Dr. Reichl notes. 

Conclusion 

How much faster do you want your 

wire bonders to run? Part of that 

answer can be covered by the question, 

“How much more are you willing to pay 

for your next wire bonder?” 

Billions upon billions of packages are 

being bonded each year and speed is 

certainly one pre-requesite for any 

assembler that hopes to derive a profit 

from his business. And while flip-chip 

processing is encroaching on the wire 

bonder’s home turf, there’s still lots of 

life remaining in this technology. i 

Contact the Editor at chipscale@gmail.com. 

32 


For more information on any advertiser’s products, please click on their link to be taken to their home page. 

INTERNATIONAL DIRECTORY OF PRODUCTION WIRE BONDERS 

Notes: Listings are printed as received from each vendor. Chip Scale Review does not warrant or represent that these products meet the specifications as printed. For detailed information, 

please visit the supplier’s web site. Issue advertisers are listed in boldface type. CM=Consult Manufacturer, NS=Data not supplied by deadline. 

Company Name 

Address 

b Phone 

> Fax 

Year Founded 

★ President 

✦ CEO 

Model 

V Introduced 

❖ Bonding Area (X, Y in mm) 

Package Leadframe 

Capabilities: 

l Length in mm 

w Width in mm 

t Thickness in mm 

✖ Bond Pitch Capability 

in µm@ 3 sigma 

W Weight in kg 

M Type and Method 

p Bond Placement 

repeatability in µm@ 3 sigma 

a Accuracy 


F Footprint 

(W x D in mm) 

H Material Handling 

S Conversion Time 

in minutes for same 

leadframe type 

Software OS 

Looping Capability 

w Maximum Wire Length in mm 

L Minimum Loop Length in µm 

✘ Applications 

1. Discretes; 2. Hybrids; 

3. ICs; 4. Laser diodes; 

5. MCMs/other modules; 

6. MEMS/MOEMS; 7. Opto/Nano 

8. Smart cards; 9. Other 

[web site] 

❉ Contact 

b Phone > Fax 

Additional Offices 

ASM Pacific Technology Ltd. 

4/F Watson Centre 

16 Kung Yip St., Hong Kong 

b +852.2619.2000 

> +852.2619.2118/9 

1975 

✦ W.K. Lee 

iHawk 

V May 2006 

❖ 54 x 65 

@leadframe width 80mm 

L 3mm depends on wire diameter 

✘ 1, 2, 5 

w >80mm 

L 80mm 

L 215.784.6284 

1975 

★✦ C. Scott Kulicke 

Maxµm ultra 

(high-performance wire bonder) 

V 2004/2005 

❖ 56 x 66 

l 90-267 w 15.2-90 

t 0.10 to 0.89 

Maxµm elite 

(automatic wire bonder) 

V 2004/2005 

❖ 56 x 66 

l 90-267 w 15.2-90 

t 0.10 to 0.89 

✖ 35µm 

W 560 

M Thermosonic/ball 

p CM 

a ±2.5µm 

✖ 60µm 

W 560 


p CM 

a ±3.4µm 

F 889 x 889 

H Standard leadframe 

and substrate, flat boat, 

tape BGA, manual 

S


INTERNATIONAL DIRECTORY OF PRODUCTION WIRE BONDERS 

Company Name 

Address 

b Phone 

> Fax 

Year Founded 

★ President 

✦ CEO 

Model 

V Introduced 

❖ Bonding Area (X, Y in mm) 

Package Leadframe 

Capabilities 

l Length in mm 

w Width in mm 

t Thickness in mm 

✖ Bond Pitch Capability 


W Weight in kg 

M Type and Method 

p Bond Placement 

repeatability in µm@ 3 sigma 

a Accuracy 


F Footprint 

(W x D in mm) 

H Material Handling 

S Conversion Time 

in minutes for same 

leadframe type 

Software OS 

Looping Capability 

w Maximum Wire Length in mm 

L Minimum Loop Length in µm 

✘ Applications 

1. Discretes; 2. Hybrids; 

3. ICs; 4. Laser diodes; 

5. MCMs/other modules; 

6. MEMS/MOEMS; 7. Opto/Nano 

8. Smart cards; 9. Other 

[web site] 

❉ Contact 

b Phone > Fax 


Oerlikon Assembly 

Equipment (formerly ESEC) 

1121 W. Warner Rd., Ste. 107 

Tempe, AZ 85284 

1967 

★ Kurt Trippacher 

WB3100optima 

V July 2006 

❖ 52 x 70 

l 100-2700 

w 15-84 

t 0.1-0.8 

✖ 35 

W 590 


p CM 

a ±2.5 

F 850 x 960 

H Leadframes, 

substrates, 

Auer boats 

S CM 

Windows 2000 

w 9mm 

L 50µm 

✘ 1, 2, 3, 4, 5, 6, 8 

[oerlikon.com] 

❉ Greg Harding 

greg.harding@oerlikon.com 

b 480.588.9833 

Orthodyne Electronics 

16700 Red Hill Ave. 

Irvine, CA 92606 

b 949.660.0440 

> 949.660.0444 

1962 

★✦ Gregg Kelly 

7200 Plus 

(dual head semiconductor bonder) 

V August 2007 

❖ 70 x 70 

l 160-260 

(110-159 requires kit) 

w 18-72 

t CM 

3600 Plus 

(large wire bonder) 

V June 2005 

❖ 250 x 150 standard 

(300 x 300 w/optional 

work table) 

l CM 

w CM 

t CM 

3700 Plus 

(small wire bonder) 

V June 2005 

❖ 250 x 150 standard 

(300 x 300 w/optional 

work table) 

l CM 

w CM 

t CM 

✖ CM 

W 682 

M Ultrasonic/wedge, 

wire or ribbon 

p CM 

a ±10µm large wire 

±5µm small wire 

✖ CM 

W 471 

M Ultrasonic/wedge, 

wire and ribbon 

p CM 

a ±10µm large wire 

✖ CM 

W 471 

M Ultrasonic/ball, 

lead, wedge 

p CM 

a ±5µm small wire 

F 1740 x 1280 

H Auer boats, 

leadframe, 

leadframe inline, 

magazine-tomagazine 

S CM 

CM 

F 680 x 1308 

H CM 

S CM 

CM 

F 680 x 1308 

H CM 

S CM 

CM 

w CM 

L CM 

✘ 1, 9: Power leadframes 

w CM 

L CM 

✘ 2, 5 

w CM 

L CM 

✘ 2, 5, 9: COB 

[orthodyne.com] 

❉ Siegbert Haumann, 

Product Manager 

siggi.haumann@orthodyne.com 

b 949.660.0440 

❉ Matt Vorona, Director of 

International Sales 

matt.vorona@orthodyne.com 

❉ Gary Silverberg, 

Director of Domestic Sales 

gary.silverberg@orthodyne.com 

Eastern Regional Office 

116 Ellsworth Ave. 

Mineola, NY 11501 

❉ Mike McKeown, 

Sales Manager 

mike.mckeown@orthodyne.com 

b 516.739.2690 

Orthodyne Electronics GmbH 

Nuernberg, Germany 

b +49.911.98813.0 

❉ Stefan Weiss, 

Managing Director 

stefan.weiss@orthodyne.de 

Palomar Technologies 

2728 Loker Avenue West 

Carlsbad, CA 92010 

b 760.931.3600 

1995 

★ Bruce Heuners 

✦ Gary Gist 

Model 8000 

(high speed Au ball bumper 

and wire bonder) 

V October 2004 

❖ 305 x 163 

l Up to entire bonding 

area 

w Up to entire bonding 

area 

t Nearly unlimited 

✖

Flip-Chip Processing Secrets: 

Saving Money and Saving Time 

Today’s equipment belongs to the next-generation, and would surprise (perhaps amaze) your father. Right: This prototype 45nm Embedded Dynamic 

Random Access Memory chip contains over 12 million bits and high-performance logic. (IBM) 

The biggest “secret” to successful, automated flip-chip production is 

the careful selection of the increasingly intelligent equipment that 

makes the technology more affordable, reliable and amazingly accurate. 

Your choice of the best tools for your applications is going to result in 

your company either saving lots of money, or—alternatively—writing a 

check for a dust-gathering behemoth that spends much of its time 

sitting in a corner like a wallflower at the prom. 

By Terrence E. Thompson, 

Senior Editor 

[tethompson@aol.com] 

Flip-chip technology (it’s a 

process, not a package type) 

owes much of its current acceptance 

to the automated equipment used to 

physically flip the chip for attachment. 

Another important factor is 

the selection of the material sets 

required. 

Since the lead-free solders now 

used require higher melting points 

than lead-based solders, it certainly 

isn't your father’s flip-chip process 

with its much more forgiving temperature 

requirements. 

36 


Laurier's M9 flip-chip die bonder 

This article looks at what works and 

what doesn’t in flip-chip technology. 

End-user and vendor tips on how to get 

the most out of your machines with 

either lead-free or tin-lead solder provide 

food for thought. A directory of 

flip-chip assembly equipment with key 

specs follows this article. 

Size Matters 

Sometimes you need to look back 

before analyzing present and future 

packaging possibilities. 

Why do flip chips continue to enjoy 

increased popularity? Likely, because 

smaller is better when an increasing 

number of mobile devices coupled with 

short consumer product life cycles dramatically 

compress the time between 

design and viable packaging solutions. 

FCs typically offer significant performance 

advantages over traditionally 

The FineTech Femto Opto-Bonder for photonic 

devices. 

packaged ICs. The formers’ shorter signal 

paths result in lower inductance, 

resistance and capacitance. 

Reflow soldering of bumped FCs is 

simpler than familiar epoxy die attach 

and wire bonding. FC technology integrates 

mechanical and electrical interconnects 

and reduces process steps. Yet, 

some flip-chip-in-package (FCIP) 

applications also use some complementary 

wire-bonding interconnects 

between ICs. 

Flip-chip assembly provides electrical 

connection of active surface, face-down 

ICs or other electronics placed on substrates, 

PWBs or carriers with conductive 

bumps on the bond pads. 

With many more affordable flip chips 

being batch-produced with wafer-level 

packaging, the technology will find its 

way into numerous package types 

whose cost-sensitivity ruled them out 

earlier. 

Better Bonders 

Paul Mescher, vice president of flip-chip 

operations at Amkor Technology, 

Chandler, Ariz., views bonder requirements 

like this: “The biggest strength of 

existing production FCIP placement 

systems today is their balance of speed 

and accuracy. 

This balance, adds Mescher, enables 

the same or “very similar systems to be 

used for a broad range of applications, 

whether it be variations in die size or 

bump pitch. 

“In addition, most (if not all) of the 

production systems have vision accuracy 

that is capable well beyond the current 

mainstream bump-pitch requirements, 

so production longevity—and therefore 

investment payback— is not a significant 

concern.” 

Mescher adds, “There are a number 

of SMT systems that can handle FC 

devices for flip-chip-on-board (FCOB) 

applications. These systems, however, 

struggle in an FCIP environment, since 

they generally have limited/non-integrated 

Datacon Technology’s 2200 evo Twin-Head Multi-Chip 

Die Bonder 

wafer-handling systems and usually sacrifice 

accuracy for speed.” 

Flip-Chip Device Trends 

The biggest technology trend within the 

FCIP market is the beginning of the 

transition to Pb-free bumping, says 

Mescher. 

“While RoHS exemptions exist for Pb 

in flip-chip bumps, the market desires 

to have a full Pb-free solution when it is 

proven technically capable of supporting 

the required reliability and electrical 

integrity,” he adds. 

“Recent improvements in Pb-free 

bumping and package materials have 

shown ability to meet the reliability 

hurdles, and this has stimulated the 

migration to Pb-free bump products,” 

says Mescher. 

The initial products qualifying in Pbfree 

bump are for consumer and gaming 

applications, with conversion expected 

to occur over the next several years. Less 

clear is the timing on conversions for 

high-reliability devices like microprocessors 

and telecom infrastructure products. 

“These applications will likely require 

years of field reliability before the 

‘brains’ of systems fully commit to Pbfree 

bumps,” Mescher believes. 

“Regardless of timing, it is now clear 

that Pb-free bumps will be a major 

technology challenge for FC products as 

we move through the next 5 to 10 years.” 


Are you sure you didn’t take my 

copy of Chip Scale Review? 

There’s no need to fight over a copy, when subscriptions 

are free for qualified readers! 

For a limited time, one-year subscriptions 

are FREE for all qualified readers, 

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It’s easy to sign up. Simply visit our 

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38 


NM-5850A die bonder from Panasonic Factory 

Solutions Company of America 

Essential: Better Solder Joints 

Kyung Moon Kim, senior manager for 

flip-chip product development, R&D, at 

STATS ChipPAC in Korea says, solderjoint 

reliability is key. “The important 

factors are proper solder flux and 

underfill materials. Flux materials must 

be compatible with the bump composition 

to ensure good solder-joint yields. 

“In addition,” he adds, “underfill 

material should be compatible with flux 

residue and die passivation layers. Low-k 

devices require a well balanced T g , modulus 

and CTE to prevent mechanical damage 

to the inner layer of the low-k device.” 

Key Application Trends 

Kim adds “key flip-chip application 

trends involve deploying multiple flipchip 

die in one package and reducing 

the overall package size with a fine 

bump pitch and a thinner profile. 

“This, in turn, drives the need for 

flip-chip bonders with features such as a 

modular platform concept for multichip 

attach with various die pick-up 

solutions, including waffle pack, wafer 

frame and reel-to-reel, and so forth.” 

These, says Kim, should be capable of 

fine bump pitches (~ below 150µm), 

smaller bump sizes and higher I/O 

counts. Next-generation die bonders 

must be capable of placing thin die 

onto thin laminate substrates, too.” 

Kim says the most significant trends 

in flip-chip technology include placing 

low-k application die for high-end devices 

(65nm in high volume manufacturing 

with 45nm under development). 

In addition, bumped-wafer thinning, 

100µm in high volume manufacturing 

with 75µm under development, are 

important. 

Other challenges include: 

• Fine bump pitch (160µm in high 

volume manufacturing with 150µm 

under development) 

• Die size (18x18mm in high volume 

manufacturing and >24x24mm 

under development) 

• Bump composition (63Sn/37Pb, 

5Sn/95Pb high lead bumps, SAC305 

Pb-free in high volume 

• Manufacturing and novel metals (Cu, 

etc.) under development) 

• Underfill processes (capillary and jet 

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Polaris Jr. bonder from Unovis Solutions (formerly 

Universal Instruments Corp.) 

turing and molded underfill for large 

die size under development) 

What’s Needed 

Prof. Herbert Reichl of the Fraunhofer 

IZM in Berlin, Germany, is convinced 

that die bonders need significant 

improvements or innovation in many 

hardware/software areas. Among them, 

he cites: 

Improved scrubbing modes, as well 

as an increase in the accuracy of pickand-place, 

better chip and substrate 

illumination. 

His list also includes secure handling 

(chip ejection from tape and pick-andplace) 

of thinned wafers and/or chips, 

as well as secure handling of UV-active 

adhesives and blue tapes. 

Offline programming is also desirable, 

as is the automatic processing of adhesives 

with high thermal conductivity, 

and therefore a high percent of fill particles. 

Active cooling of the bond head, 

says Prof. Reichl, will offer increased 

work life (pot time) for adhesives. 

His list also includes large area assembly 

for 200mm/300mm, faster tool 

change, and 3D stacking capability. 

In joining, desired items include 

temperature capability up to 450°C, fast 

heat ramp (>100 K/seconds), fast and 

sensitive force application, self-alignment 

capability and fluxless bonding 

and fast cooling. 

The Demand is Expanding 

E. Jan Vardaman, president of market 

research firm TechSearch International 

Inc., Austin, Texas, says, “The demand 

for both flip-chip and wafer-level packages 

is expanding for a wide range of 

OEM products.” 

She projects a compound growth rate 

of more than 24 percent for combined 

solder flip chip and wafer-level packaging 

through 2010, which includes gold 

and solder bumping, as well as WLP. 

The key drivers for flip-chip applications 

continue to be performance and 

form factors, notes Vardaman. Flip-chip 

interconnect is expanding into many 

device types, ranging from high performance 

logic to a variety of devices 

found in wireless products. 

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40 


Close-ups of a 300mm silicon test wafer made using a new 45nm process 

technology. Can WLP be far behind? (Intel Corp.) 

An increasing number of suppliers of 

ASICs, field programmable gate arrays 

(FPGAs), DSPs, chipsets, graphics, and 

microprocessors are expanding their use 

of FCIP. The limiting factor in the 

greater expansion of flip chip has been 

the shortage of laminate substrates, but 

this situation should improve dramatically 

in 2007, Vardaman says. 

Larger Flip Chips, Too 

WLPs have typically been used for low 

pin count (≤50 I/O) applications, 

including analog devices such as power 

amplifiers, battery management devices, 

MOSFETs, image sensors, controllers, 

memory, and integrated passives, notes 

Vardaman. 

However, many companies plan to 

use WLPs for higher pin count applications 

(≥100 I/O), including analog parts 

with larger die sizes. The growth of LCD 

TVs is an important driver for gold 

bumping. Gold bump demand continues 

to be dominated by LCD driver ICs, 

but an increasing number of gold studbumped 

devices are also shipping. 

Increased 

Functionality 

Manfred 

Glantschnig of 

Datacon Technology 

GmbH, Austria, 

notes that an 

increasing variety of 

functions and a 

shorter time-tomarket 

for innovative 

products are 

often only economically 

viable with a 

mix of technologies 

as a system-in-apackage 

(SiP). 

The most suitable 

modern manufacturing 

equipment 

for this is based on 

modular platform 

concepts of proven 

device structures with increased productivity, 

extensive flexibility, and provisions 

for the future, thanks to a variety 

of customizable extension options, 

even after initial delivery. 

Glantschnig notes that, “despite their 

increasing functionality, modern electronic 

devices are becoming smaller and 

smaller, reaching the market in evershorter 

product cycles, and are subject 

to strong cost pressures.” 

This applies, for example, to cell 

phones and other wireless devices that 

contain many features, including power 

amplifiers, GPS receivers, Bluetooth 

communications, camera modules, and 

miniature hard disks. 

In the consumer segment, this means 

MP3 players and memory cards, while 

examples from medical electronics 

include hearing aids and implants. 

Automotive electronics consume a wide 

variety of sensor modules and controllers 

for power train and driver assistance. 

Technology Mix 

Often these kinds of systems are only 

economically viable with a technology 

mix in which each subfunction is 

implemented in a particularly suitable 

technology, says Glantschnig. 

Examples include image sensors as a 

CMOS surface array (for the visible 

spectrum) or InGaAs array (for near 

infrared), MEMS for measuring transducers, 

or GaAs for microwave transmission 

and short-range radar. Because 

such differing technologies can hardly 

be combined as a system-on-a-chip 

(SoC), only SiPs can be considered here. 

Future-Proofing Bonders 

Glantschnig insists that this spectrum of 

diverse requirements will be best served 

with machine evolution, which can 

deliver revolutionary results. 

To begin with, keep field-proven features, 

including modular machine concepts; 

high precision, small footprints 

and an uptime availability of at least 98 

percent. Innovative reconfiguring can 

involve a separate dispense system 

which works in parallel with the standard 

bonder/dispense system for direct 

assembly and flip chips, thus considerably 

increasing the throughput. 

Conclusion 

There is a continuing path of innovation 

in flip-chip manufacturing, OEM 

applications and and bonding methodologies. 

The rapidly growing use of WLP to 

produce packaged FCs is well underway, 

which should lower their costs. The 

challenge for bonding equipment vendors 

is to look for better ways of placing 

FCs accurately and affordably, while 

meeting volume production requirements. 

Soon, high-k ICs will join the dominant 

low-k dielectric devices being 

assembled now. This may or may not be 

a problem, but it will certainly present 

new challenges and opportunities for 

equipment makers. i 

Contact Terry at tethompson@aol.com. 


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42 



INTERNATIONAL DIRECTORY OF FLIP CHIP & DIE ATTACH BONDERS/ALIGNERS 

Notes: Listings are printed as received from each vendor. Chip Scale Review does not warrant or represent that these products meet the specifications as printed. For detailed information, 

please visit the supplier’s web site. Issue advertisers are listed in boldface type. CM=Consult Manufacturer. 

Company Name 

Address 

b Phone 

> Fax 

Year Founded 

Model 

V Introduced 

✖ Level of Automation 

A=Automated 

S=Semi-Automated 

P Product Type 

FC=Flip Chip Attach/Bonding 

DB=Die Attach/Bonding Equip. 

W Wafer Size in mm 

d Die Edge Length Capability 

F Footprint width by depth 

p Placement Accuracy 


A Alignment Accuracy 


m Machine Vision 

Z Z-Axis range in mm and max. force 

P Primary Applications 

s Secondary Applications 

✘ Bonding Methods 

A=Adhesive; ACF=Anisotropic Conductive Film; 

E=Eutectic; F=Flip Chip; P=Preform; S=Solder; 

O=Other 

p Special Features 

[web site] 

❉ Technical Contact 

b Phone > Fax 


Alphasem GmbH 

Division of Kulicke & Soffa 

Andhauserstrasse 52 

8572 Berg, TG, Switzerland 

b +41.71637.63.63 

> +41.71.637.63.64 

1979 (Founded in 1979 as 

Gustav Wirz AG. Renamed 

Alphasem in 1985.) 

Easyline 8088 

V 2005 

✖ A 

P DB 

W Up to 200mm 

d 0.25 to 20.3mm 

F 90 x 110cm 

p 25 

A CM 

m CM 

Z CM, 10N max. force 

P MEMS 

s IC 

✘ A 

p Die attach onto wide-area 

ceramic substrates 

[alphasem.com] 

❉ Alphasem GmbH (Sales) 

sales.eu@alphasem.com 

USA: Alphasem Corp. 

150 E. Alamo Dr., Chandler, AZ 85225 

❉ gisler.w@alphasem.com 

b 480.892.9021 > 480.892.9058 

China: Alphasem (Suzhou) Co. Ltd. 

Suite 2304 Pan Pacific Building 

No. 1221 Yan An West Road 

Shanghai 200050 China 

❉ shan.d@alphasem.com 

b +86.21.5238.70.11 

> +86.21.5238.70.13 

ASM Assembly 

Automation Ltd. 

4/F Watson Centre 

16 Kung Yip Street 

Kwai Chung, Hong Kong 

b 408.451.0800 (USA) 

> 408.451.0808 (USA) 

1975 

AD9012A 

12" Flip Chip Bonder 

V 2006 

✖ A 

P FC 

W 200 to 300mm 

d 250µm to 25mm 

F 221 x 136cm 

p ±10 

A CM 

m Yes 

Z CM, 5kg max. force 

P ICs, RF 

s Die attach 

✘ A, C4, F, S, T, O=Bumps, stud 

bump, thermosonic flip-chip, 

thermocompression, NCP, 

solder reflow 

p Built-in dispensing system 

[asmpacific.com] 

❉ Jerry Dellheim 

b 408.451.0800 

> 408.451.0808 

San Jose, CA; Phoenix, AZ 

EV Group 

DI Erich Thallner Strasse 1 

4782 St. Florian/Inn, Austria 

b +43.7712.5311.0 

> +43.7712.5311.4600 

1980 

EVG540C2W 

V CM 

✖ A, S 

P FC, DB 

W 50 to 300mm 

d CM 

F CM 

p CM 

A CM 

m CM 

Z CM 

P ICs, MEMS, Optical/photonic 

s CM 

✘ A, E, T, O=Fusion bonding, 

polymer 

p Hermetic sealing, good known die 

[evgroup.com] 

❉ Thomas Fodermeyer 

info@evgroup.com 

b +43.7712.5311.0 

Finetech GmbH & Co. KG 

Wolfener Str. 32/34 Haus L 

12681 Berlin, Germany 

b +49.30.936681.0 

> +49.30.93668.144 

1992 

FINEPLACER Pico AMA 

(Automatic Micro Assembler) 

V 2006 

✖ A 

P FC, DB 

Opto-Bonder Femto 

V 2007 

✖ CM 

P FC, DB 

W ≤200mm 

d 0.1 to 85mm 

F 150 x 90cm 

p 5 

A 0.25 

m Yes 

Z 10mm, 500N 

W Up to 200mm 

d 0.1 to 100mm 

F 130 x 90cm 

p 5 

A 0.25 

m Optional 

Z 10mm, 500N 

P ICs, MEMS, opto, RF 

s CM 

✘ A, E, F, P, S, T, O=stud, 

thermosonic 

p CM 

P Opto 

s CM 

✘ CM 

p CM 

[finetechusa.com] 

❉ Chris Underhill, General Manager 

chris@finetechusa.com 

b 480.893.1630 

> 480.893.1632 

USA: Finetech Inc. 

1334 E. Chandler Blvd. 

5D 5D22, Phoenix, AZ 85048 

b 480.460.8777 

> 480.460.8778 

Laurier Inc. 

(Besi Die Handling Division of 

BE Semiconductor Ind. NV) 

10 Tinker Ave. 

Londonderry, NH 03053 

b 603.206.4800 

> 603.226.4242 

1986 

Laurier M9 ultra high 

accuracy flip chip die 

bonder 

V CM 

✖ SA 

P FC 

W CM 

d CM 

F CM 

p ±0.5 

A CM 

m Yes 

Z CM, 50kg 

P Semiconductor and optical 

component assembly processes 

s CM 

✘ A, S, O=Cold compression, 

thermocompression, adhesive 

cure, optional ultrasonic 

p CM 

[laurierinc.com] or [besidiehandling.com] 

❉ Doris Ager, Worldwide Marketing 

Communications 

doris.ager@datacon.at 

Innstrasse 16, 6240 Radfeld, Austria 

b +43.5337.600.128 

Mühlbauer AG 

Josef Mühlbauer Platz 1 

93426 Roding, Germany 

1981 

DS 10000/CM 

Flip Chip Die Sorting 

V 2004 

✖ A 

P FC, DB 

FCM 10000/CM 

Flip Chip Die Bonding 

V 2004 

✖ A 

P FC, DB 

W CM 

d 0.3mm to CM 

F CM 

p CM 

A CM 

m Yes 

Z CM 

P ICs, MEMS, RF 

s Die sorting 

✘ A, ACF, FC, P, S, T, O=Bumps, 

(solder, plated, electroless 

nickel-gold), stud bump 

p CM 

[muhlbauer.com] 

❉ Gerald Steinwasser, General Manager 

info@muhlbauer.com 

USA: Mühlbauer Inc. 

725 Middle Ground Blvd. 

Newport News, VA 23606 

b 757.873.0424 

> 757.873.0485 


INTERNATIONAL DIRECTORY OF FLIP CHIP & DIE ATTACH BONDERS/ALIGNERS 

Company Name 

Address 

b Phone 

> Fax 

Year Founded 


Model 

V Introduced 

✖ Level of Automation 

A=Automated 

S=Semi-Automated 

P Product Type 

FC=Flip Chip Attach/Bonding 

DB=Die Attach/Bonding Equip. 

W Wafer Size in mm 

d Die Edge Length Capability 

F Footprint width by depth 

p Placement Accuracy 


A Alignment Accuracy 


m Machine Vision 

Z Z-Axis range in mm and max. force 

P Primary Applications 

s Secondary Applications 

✘ Bonding Methods 

A=Adhesive; ACF=Anisotropic Conductive Film; 

E=Eutectic; F=Flip Chip; P=Preform; S=Solder; 

O=Other 

p Special Features 

[web site] 

❉ Technical Contact 

b Phone > Fax 


Newport Corp. 

101 Billerica Ave. 

N. Billerica, MA 01862 

b 978.667.9449 

> 978.667.6109 

1969 

MRSI-M5 

V 2005 

✖ A 

P FC, DB 

W 100 to 200mm 

d 0.2µm to 150mm 

F 22 x 178cm 

p 5 A 2 

m No 

Z 0 to 40mm, 10kg 

P ICs, MEMS, opto/photonic, RF 

s Microwave 

✘ A, E, F, P, S, O=Polymer, stud bump 

p Complex die attach, 

ambient to 450° 

[newport.com] 

❉ Dan Crowley, Director of Sales 

sales@ma.newport.com 

1791 Deere Ave., Irvine, CA 92606 

Palomar Technologies Inc. 

2728 Loker Avenue West 

Carlsbad, CA 92010 

b 760.931.3600 

> 760.931.5191 

1995 

6500 

V 2003 

✖ A 

P FC, DB 

W 1 to 300mm 


F 96.5 x 122cm 

p 1.5 to 3.5 

A 1.5 to 3 

m Yes 

Z 0 to 25.4mm, 10kg 

P ICs, MEMS, opto/photonic, RF, 

complex hybrid/MCM, high reliability 

s Space based modules, automotive, 

life sciences, computer and 

peripheral 

✘ A, ACF, C4, E, F, P, S, T, O=Polymer 

p Extreme accuracy, high flexibility 

[palomartechnologies.com] 

❉ Bradley K. Benton 

bbenton@bonders.com 

3500-III 

V 2006 

✖ A 

P FC 

W 1 to 300mm 

d 0.2 to 300mm 

F 152 x 106cm 

p 5 to 10 

A 1.5 to 3 

m Yes 

Z 0 to 50mm, 50kg 

P ICs, MEMS, opto/photonic, RF, 

complex hybrid/MCM, high reliability 

s Space based modules, automotive, 

life sciences, computer and peripheral 

✘ A, ACF, C4, E, F, P, S, T, O=Polymer, 

copper bumps, thermocompression 

p Large area, very flexible, accuracy 

Panasonic Factory 

Solutions Company of 

America 

909 Asbury Dr. 

Buffalo Grove, IL 60089 

1988 

FCB3 

V 2005 

✖ A 

P FC 

W 75 to 300mm 

d 1 to 20mm 

F 160 x 198cm 

p 3 

A 3 

m Yes 

Z CM, 50kg 

P ICs 

s LEDs 

✘ A, ACF, C4, F, S, T, O=Stud bumps, 

copper bumps, discrete bumps, 

thermosonic 

p High force head with high 

accuracy 

[panasonicfa.com] 

❉ Gene Dunn, Engineering Manager 

b 847.495.6100 

FCX 501 

V 2005 

✖ A 

P FC 

W 75 to 200mm 


F 100 x 100cm 

p 10 

A 10 

m Yes 

Z CM, 2kg 

P RF 

s LEDs 

✘ A, ACF, C4, F, S, T, O=Stud bumps, 

thermosonic 

p Heated head for gold/gold to 

organics 

Semiconductor 

Equipment Corp. 

5154 Golman Ave. 

Morpark, CA 93020 

b 805.529.2293 

> 805.529.2193 

Yamaha i-CUBE II 

V CM 

✖ A 

P FC, DB 

W 50mm to CM 

d CM 

F CM 

p ±20 A ±12.5 

m Yes 

Z CM, 1 to 49N 

P Die placement, MCP, SIP 

s CM 

✘ O=Non-contact dispensing 

p Two pick and place heads with a 

vacuum tool and an adhesive 

dispenser and control force. 

[semicorp.com] 

❉ Don Moore, President 

sales@semicorp.com 

b 805.529.2293 

Shinkawa Ltd. 

2-51-1 Inadaira 

Musashimurayama-shi 

Tokyo, Japan 208-8585 

b +81.42.560.1241 

> +81.42.560.7322 

1959 

SPA-400 

V 2006 

✖ A 

P DB 

W 150 to 300mm 

d 0.8 to 25mm 

F 137 x 120cm 

p 20 

A 1/4 pixel 

m Yes 

Z 0 to 5mm, 15N (50N option) 

P ICs 

s CM 

✘ T 

p High accuracy die placement 

[shinkawa.com] 

❉ Doug Day, General Manager 

d_day@shinkawausa.com 

b 480.831.7988 

USA: Shinkawa USA Inc. 

1930 S. Alma School Rd. 

Suite D-107, Mesa, AZ 85210 

Siemens 

(Acquired F&K Delvotec 

Bondtechnik GmbH’s die bonders) 

Data not supplied Data not supplied Data not supplied 

Data not supplied 

SUSS MicroTec SAS 

Division of SUSS MicroTec AG 

131 Impasse Barteudet 

74490 Saint Jeoire, France 

b +33.450.35.38.03 

> +33.450.35.38.27 

1975 

SUSS FC300 

High Force Device Bonder 

V 2006 

✖ A, S 

P FC, DB 

W 300mm dia. or 0.2 to 200mm 


F 210 x 196cm 

p 0.5 

A 0.1 

m Yes 

Z 100µm to 7mm, 4,000N 

P ICs, MEMS, opto/photonic, RF 

s IR-FPA, micromechanics assembly 

✘ A, ACF, E, F, P, S, O=Polymer, 

stud bump, thermosonic 

p Room temperature and thermocompression 

high force, can 

perform a non-bonding application 

[suss.com] 

❉ Gilbert Lecarpentier, 

Business Manager 

glecarpentier@sussmicrotec.fr 

Unovis Solutions 

(Universal Instruments and 

Hover-Davis) 

P.O. Box 5304 

Binghamton, NY 13902 

2006 

Advantis XS 

V CM 

✖ CM 

P FC, DB 

W 50.8 to 508mm 

d CM 

F 167.6 x 167.6cm 

p ±9 

A CM 

m Yes 

Z CM 

P FC, bare die, ICs, area array 

s CM 

✘ CM 

p CM 

[unovis-solutions.com] 

❉ Bob Lamanna, 

Director of Sales–Americas 

b 607.779.5118 

> 607.765.4429 

44 


The Challenge of Packaging Small Power Devices 

Driven by space-critical end uses, the 

demand for smaller, thinner devices is 

dictating the development of packaging 

and interconnections for discrete 

power semiconductors. Until recently, 

fine wire ball bonding and Cu strap 

attachment were the main interconnect 

techniques for power packages smaller 

than the TO-252. A new, large aluminum 

ribbon bonding process, meanwhile, 

has overcome past size restrictions to 

enable the use of this technology, 

which overcomes weaknesses in 

traditional techniques. 

By Dr. Christoph Luechinger and 

Siegbert Haumann, Orthodyne 

Electronics Corp., Irvine, Calif. 

[orthodyne.com] 

TO packages are recognized as 

the industry standard worldwide 

for medium-power discrete devices. 

Over the past 10-15 years, there has 

been a steady shift from the TO-220 

package to the smaller TO-252 

(DPAK), see Figure 1. 

Trends 

Large aluminum wire bonding (5 to 20 

mils) is the main interconnect technique 

for these packages. Ongoing developments 

in high-performance wire bonding 

equipment and expertise enable these 

parts to be interconnected reliably, with 

very high yield at low cost. 

The main interconnect method for 

smaller, lower-power packages, especially 

the SO-8, is gold ball bonding with wire 

diameters in the range of 1 to 3 mils. 

Advances in power chip technology 

enabled a trend towards smaller packages, 

with the same or similar current 

capabilities that the larger TO-XXX 

packages offered only a few years ago, a 

trend that makes sense economically. 

The demand for smaller, thinner devices and packages is the major driver for the power semiconductor market. 

For constant cost-per-wafer, the price 

per die decreases with die size. A smaller 

(or more efficient) die permits the use of 

a smaller package, which means less material 

per device, and therefore lower cost. 

Smaller devices require less PWB 

area, contributing to cost savings at the 

system level. If all this enables new 

applications, economy-of-scale will 

bring additional cost benefits. 

Portable applications drove requirements 

that were difficult to achieve by 

the existing packages. They require very 

efficient power devices of very small 

size. In addition, high-end applications 

in telecom and computing require the 

best possible electrical and thermal performance, 

together with a small footprint. 

These needs spurred significant 

efforts to develop new packaging and 

interconnect designs, including wirebond-free 

designs. 

While wire bond-free designs address 

performance requirements, most are 

proprietary, thus non-standard and their 

manufacturing costs remain questionable. 

Market Needs 

While performance is an initial enabler, 

costs must be in line with market needs; 

thus the drive to standard, non-proprietary 

packages and interconnect technologies 

that provide good electrical 

performance, the needed footprint and 

reliability at a reasonable cost. Leadless 

SO-8 or PQFN-type packages fulfill 

these requirements. 

Available Interconnects 

Fine gold-wire bonding becomes less 

and less effective, especially in small 

power packages where large wire diameters 

are desired. 

The high material cost runs counter 

to the need to increase the interconnect 

cross-section to accommodate higher 

current requirements. Its less expensive 

sibling, copper wire bonding, reduces 

wire material cost and can improve 

electrical performance. 

Copper’s material properties (hardness, 

oxidation behavior), however, add additional 

(process, yield) cost. An area-bonded 


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46 


Figure 1. This figure illustrates the trend in TO 

packages over the past 10-15 years. 

copper strap (clip) enables the desired 

electrical performance, but cost, flexibility 

and reliability remain issues. 

The use of large aluminum wire in 

small power packages, appreciated in 

larger power packages due to aluminum’s 

flexibility, reliability and low cost, only 

applies to some select applications. Its 

use is limited to wire sizes on the lower 

range of its capabilities due to package 

size constraints. 

For a broad range of mainstream 

applications to benefit from recent 

developments in power chip technology, 

an overall effective interconnect 

technology with performance sufficient 

and cost low enough for the majority of 

applications is needed. 

Evolutionary Extension 

A recent development offers the ultrasonic 

bonding of large aluminum ribbon 

in the range of 20x4 mils up to 80x10 

mils, and is an evolutionary extension of 

large aluminum wire bonding (patents 

are pending). 

The round cross-section of the wire is 

replaced by the rectangular cross-section 

of the ribbon. Aluminum material composition 

and mechanical properties are 

equivalent to large aluminum wire. The 

change in the geometry of the crosssection 

diminishes the horizontal flexibility, 

but increases the vertical flexibility 

of the interconnect. 

Horizontal flexibility, the ability to 

bond wires under large, forced angles, is 

important to interconnect configurations 

with a complex structure such as TO 

Figure 2. SO-8 device bonded with 40 x 4 mil aluminum 

ribbon. 

packages and multi-chip applications. 

Vertical flexibility—the decoupling of 

thickness and width—enables the user 

to select ribbon thickness and width 

independently. The result allows the 

user to fit a large interconnect crosssection, 

with a minimum number of 

ribbons, into the space provided by the 

application. 

Figure 2 illustrates why the layout of 

small power packages such as the standard 

SO-8 or PQFN-type packages is 

perfectly suited for this new develop- 


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48 


Figure 3. This is a next-generation dual-head 

ultrasonic bonder that can be configured for ribbon, 

wedge or wire bonding. 

ment in aluminum bonding. The wide 

source lead along a large portion of the 

heat sink and die allow the ribbon to 

cover a large portion of the die with a 

minimal number of straight ribbons. 

Performance 

Table 1 displays the electrical resistance 

for 1mm length of 40x4 mils aluminum 

ribbon at approximately 0.26mΩ, while 

it is approx. 11.35Ω or nearly 43x higher 

for a 1mm length of 2 mils gold wire 

or approx. 8.39Ω or nearly 32 times 

higher for 1mm length of 2mil Cu wire. 

But the maximum number of fine 

wires that can be bonded in a standard 

SO-8 package is limited by the size of 

the source lead, depending on the width 

of the lead to 20/22 wires for 2mil 

diameter. 

For a die with the approximate 

dimensions 140x100mils and a typical 

source metallization thickness of 4µm, 

the interconnect resistance (main loop 

plus spreading) of a configuration with 

two parallel 40x4mil ribbons with 2 

stitches on the die each is approx. 

0.5mΩ, which would be the equivalent 

of 18 copper wires of 3mil diameter, the 

maximum number of wires that fits 

into this package. Considering that each 

interconnect represents a potential yield 

loss, this is an attractive alternative. 

Table 1. Wire-to-ribbon conversion for equal electrical resistance at identical loop length 

20x4mil 30x4mil 40x4mil 50x5mil 60x4mil 60x6mil 

Ribbon Al Al Al Al Al Al 

Wire Resistance/mm length 0.52 0.35 0.26 0.17 0.17 0.12 

2mil Al 13.32 25.5 38.2 50.9 79.6 76.4 114.6 

3mil Al 5.92 11.3 17.0 22.6 35.4 34.0 50.9 

4mil Al 3.33 6.4 9.5 12.7 19.9 19.1 28.6 

5mil Al 2.13 4.1 6.1 8.1 12.7 12.2 18.3 

6mil Al 1.48 2.8 4.2 5.7 8.8 8.5 12.7 

8mil Al 0.83 1.6 2.4 3.2 5.0 4.8 7.2 

2mil Au 11.35 20.0 30.0 40.0 62.5 60.0 90.0 

3mil Au 5.04 8.9 13.3 17.8 27.8 26.7 40.0 

2mil Cu 8.39 15.9 23.9 31.8 49.7 47.7 71.6 

3mil Cu 3.73 7.1 10.6 14.1 22.1 21.2 31.8 

4mil Cu 2.10 4.0 6.0 8.0 12.4 11.9 17.9 

5mil Cu 1.34 2.5 3.8 5.1 8.0 7.6 11.5 

6mil Cu 0.93 1.8 2.7 3.5 5.5 5.3 8.0 

(Calculations are based on the electrical resistivity Ω of the materials in typical bond-wire quality: ρ Al = 2.7x10-6 Ωcm; ρ Au = 2.3x10-6 

Ωcm; ρ Cu = 1.7x10-6 Ωcm. Note that the values can vary due to dimensional variations of the ribbons and wires.) 

If a device is operated at higher frequencies, 

inductance and skin effect in 

the interconnect need to be considered. 

Inductance primarily affects the 

switching behavior of a device, while 

skin effect reduces the effective interconnect 

cross-section, causing a significant 

resistance increase—and therefore 

power loss—at higher frequencies. 

Inductance is mainly a function of the 

geometry of the interconnect, length 

being the main factor. 

Ribbon offers inductance similar to 

strap bonding, but with significant performance 

benefits compared to any 

round-wire alternative. 

Reliability 

Although configurations with large 

bonded joints on the back and top sides 

of the die can be made reliable by 

appropriate design and material choice, 

configurations with wire or ribbon 

interconnects on the top side of the die 

are inherently more forgiving, and 

therefore more reliable, under operating 

conditions. 

In several evaluation activities, standard 

and leadless SO-8 devices passed 

typical reliability tests, specifically (a) 

temperature cycling (500 cycles @ - 

65°C/+150°C), (b) high-temperature 

storage (1,000 hours @ 175°C), (c) pressure 

cooker test (168 hours @ 

Ta=121°C, RH=100%, 15PSIG), and (d) 

Moisture Sensitivity Level 2 (MSL2) 

with standard preconditioning, all without 

any ribbon bonding-related failure. 

With their monometallic bond on the 

die, aluminum ribbon-bonded parts 

enable reliable operation up to chip 

junction temperatures of 175°C, if the 

gate is also bonded with an aluminum 

wire—a requirement in automotive 

applications. 

Cost 

All the different interconnect technologies 

are weak in at least one cost category. 

The high wire material cost is the main 

weakness of gold ball bonding. At 

$500/ounce, the gold material cost per 

device with approximately 22mm total 

wire length is $0.017 for 2 mils gold 

wire, and $0.030 for 2.75mil gold wire. 

Cost of 2 x 40 x 4 mils aluminum ribbon 

in corrosion resistant quality and 

approximately 2 x 3.5mm length is 

about $0.020 at low order volumes. 

An area contact design, copper strap, 

for example, demands a non-standard 

metallization that requires additional 

process steps at the wafer level, adding 

an additional cost of about $20/wafer. 

Chip Scale Review ■ March 2007 ■ [ChipScaleReview.com] 

49

10 GREAT REASONS 

TO BE IN SAN JOSE ON SEPTEMBER 17, 18 AND 19: 

1 

2 

3 

4 

Fourth International 

Wafer-Level Packaging 

Conference, Wyndham Hotel. 

Half-day workshops 

taught by experts on 

September 17. 

More exhibits than you 

can shake a stick at on 

September 18-19. 

Annual Thursday panel 

on the state of packaging 

with the industry’s wisest 

forecasters! 

5 

6 

7 

8 

Lots of technical presentations 

covering everything packaging 

and test guys need to know 

about on September 18-19. 

Free parking at the 

Wyndham Hotel located close 

to the San Jose International 

Airport. 

Great place to meet 

your vendors, your customers, 

your friends, etc. 

Register three people 

from your company and the 

fourth is FREE! 

9 

10 

11 

12 

Special rates at the 

Wyndham for attendees. 

Register early and get our 

early bird discount. 

Plenty of sun in 

San Jose! 

Special keynote dinner with exciting 

speaker (soon to be announced). 

SA N 

JOSE, 

CALIFO R NIA 

(There are so many reasons to be in San Jose at the 

Conference, we couldn’t keep it to just 10!) 

Jointly presented by: 

INTERNATIONAL WAFER-LEVEL PACKAGING CONFERENCE 

Platinum Sponsors: 

Gold Sponsors: 

S E P T E M B E R 

1 7-1 9, 

2 0 0 7 

Visit www.smta.org/iwlpc for more information.

For a 150mm wafer with dice of 6mm 2 

size the additional cost is about 1¢ per 

device. 

A strap specific to one die is inflexible 

and therefore costly. One strap-type for 

several similar die sizes, limits the electrical 

performance, making such 

designs attractive for high-performance 

applications, but less competitive for 

mainstream applications. 

The cost of copper wire is about 10x 

lower than for gold wire with the same 

dimensions. However, the copper ball 

bonding process provides a lower yield as 

well as significantly lower process speed 

compared to the gold ball bonding process. 

Copper’s material properties require 

special material handling and packaging 

including a cover gas to prevent the 

copper from oxidizing during and after 

flame-off. Despite these measures, the 

process seems to remain rather sensitive, 

especially for cratering when bonding 

over the active area. 

Gentle Process 

In contrast, bonding a soft aluminum 

ribbon is a very gentle process, due to 

the geometry; it is potentially even gentler 

than aluminum wire bonding, 

known to be best suited for bonding 

over active area. 

Additionally, aluminum ribbon configurations 

only require a few bonds on 

the die, offering much better conditions 

for minimal bond yield loss, compared 

to copper wire bonding. 

Table 2 presents an overview of estimates 

for electrical performance, material 

cost and productivity for some 

select configurations for the standard 

SO-8 package. 

Conclusions 

Large aluminum ribbon bonding is an 

evolutionary improvement over large 

aluminum wire bonding. It preserves 

most strengths of that technology and 

adds new ones, making it very effective 

in interconnecting SO-8 and smaller 

Die Size 

Range 

Typical Die 

Size 

Layout for 

Typical Die 

Size 

Electrical 

Performance 

Material 

Cost 

Table 2. Overview for performance characteristics of two sample die 

configurations for the standard SO-8 package 

Length 120mil, width 70mil for DS 

9mm 2 (Example: 140mil x 100mil) 

22 x 2mil Au: 1.6mΩ (1) 

14 x 2.75mil Au: 0.8mΩ 

18 x 3mil Cu: 0.5mΩ (1) 

22 x 2mil Au: 2.5¢ (4) 

14 x 2.75mil Au: 3.0¢ (4) 

18 x 3mil Cu: 0.3¢ (5) 

Productivity 1,500h -1 , per head (5) 

Assumptions: Values for electrical on-resistance are for 10V gate drive, estimated from data for the device resistance. 

(1) Estimated or extrapolated from measurements on similar configurations; (2) Measured. SS = Single Stitch 

on the die, DS = Double Stitch, TS = Triple Stitch; (3) Al ribbon cost at low material order quantities; (4) Au wire 

cost at Au price of $500 per ounce.; (5)Estimate; (6) Typical, based on a 5-row matrix frame. 

PQFN power packages. 

Aluminum ribbon bonding offers 

better electrical performance than ball 

wedge bonding gold at a much lower 

cost. It offers comparable electrical 

performance to copper wire bonding 

at comparable cost. When bonding over 

active areas, its gentle bond process 

enables a higher yield than copper wire 

bonding. Electrical and thermal performance 

is comparable to the performance 

of copper strap bonding but offers 

lower cost and higher flexibility. In 

addition, the monometallic aluminumaluminum 

system on the die enables 

reliable operation up to 175°C chip 

junction temperature. 

All of the above strengths are possible 

with package layouts that follow established 

standards and do not require 

specific proprietary package and interconnect 

designs. Therefore, aluminum 

ribbon bonding allows the use of wellknown 

processes and equipment. 

In summary, aluminum ribbon bonding 

is the most attractive interconnect 

technique for small power packages for 

mainstream applications which require 

2 x 40 x 4mil 

DS: 0.5m?? 

2 x 40 x 4mil 

Al: 0.2¢ (3) 

~1,800h -1 , per 

head (6) 

Length 70mil, width 40mil for SS, 70mil for DS 

4.5mm 2 (Example: 100mil x 70mil) 

5mil Cu strap: 0.5mΩ 

7 x 2mil Cu: 4.5mΩ (2) 

7 x 2mil Cu: 0.1¢ (5) 

7 x 2mil Au: 0.6¢ (4) 

~3,200h -1 , per head (5) 

1 x 40 x 4mil 

DS: 1.1Ω (2) 

1 x 60 x 4mil 

DS: 0.7mΩ (1) 

1 x 60 x 4mil 

Al: 0.1¢ (3) 

~3,200h -1 , 

per head (6) 

good electrical performance and reliability 

at reasonable cost. i 

Dr. Luechinger received his master’s and 

Ph.D. degrees in physics from ETH Zurich 

and a master’s degree in technology management 

from the University of Maryland. 

In 1999, he joined Orthodyne Electronics 

as strategic development manager, responsible 

for the development of improved 

interconnect techniques for power electronics. 

Earlier, he served with ESEC in 

Cham, Switzerland, responsible for its soft 

solder technology product line. 

[christoph.luechinger@orthodyne.com] 

Mr. Haumann received his masters 

degree in international marketing from 

the Export Academy in Reutlingen, 

Germany, and a degree in mechanical 

engineering from the Fachhochschule in 

Konstanz, Germany. He joined Orthodyne 

Electronics in 1995 and is responsible for 

product marketing. Prior to joining 

Orthodyne, he served with Robert Bosch 

GmbH in Germany, responsible for a 

number of automated production lines 

for automotive electronics. 

[siegbert.haumann@orthodyne.com] 


51

Ongoing Migration to Finer WLCSP Pitches 

By Manuel H. Mere, California Micro Devices [cmd.com] 

Vice President, Operations and Information Systems 

Since early 2001, California Micro Devices has shipped 

close to two billion units of WLCSP products. 

The bulk of these shipments has been at 0.50mm 

sphere pitches, which is the current industry standard. 

However, for reasons of reduced form factor and 

lower cost, an industry transition is in progress to 

finer pitch WLCSPs with 0.40mm pitch appearing to 

be the next standard. 

Achieving Lower Cost 

Although WLCSP cost models are more complex, the 

transition to 0.4mm pitch will deliver more value to 

the customer, since—at a first approximation—the 

cost per unit for the same function is a function of 

the square of the pitches. 

The die size of CMD’s Application Specific 

Integrated Passive (ASIP) devices in WLCSP format 

tends to be limited by the sphere pitch. Therefore, as 

the pitch is reduced, the die per wafer increases. As 

the basic wafer cost remains constant, the resulting 

unit cost will show a significant reduction. 

Improved Robustness 

Some customers have shown a reluctance to embrace 

WLCSP due to concerns about the potential for die 

cracking and chipping that may occur with adverse 

handling in manufacturing. 

The migration to finer pitch WLCSP devices helps 

to resolve these concerns. Without going into the 

mechanical aspects of the devices or our internal test 

methods, our data shows that the inherent strength 

of the 0.4mm pitch WLCSP product improves when 

compared to larger 0.5mm pitch WLCSP products. 

Earbed Rewards 

From an OEM perspective, utilizing 0.4mm pitch 

WLCSP devices requires a more evolved manufacturing 

technique. Challenges include the need to 

handle and place smaller components and to perform 

more difficult routing. 

Nevertheless, those companies that are able and 

willing to make the investment in time and effort 

The transition to 0.4mm CSPs will provide greater value to customers. 

should benefit from lower cost, a smaller form factor 

and a more robust component. 

From an OEM perspective, utilizing 

0.4mm pitch WLCSP devices requires a 

more evolved manufacturing technique. 

Discipline, world-class manufacturing organizations 

will embrace the next generation of WLCSP 

offerings; the laggards will be at an economic disadvantage. 

The Trend Is Clear 

The trend towards the tighter WLCSP pitches is very 

clear, since these pitches will deliver lower cost, 

smaller footprint and improved robustness. At CMD 

we expect the volume transition between 0.5 and 

0.4mm will occur in late 2007 and 2008. i 

■ Amkor Technology Inc. 

■ ASE (US) Inc. 

■ California Micro Devices 

■ CSP Plc. 

■ Fairchild Semiconductor 

■ Flip Chip International 

■ Intersil 

■ Maxim Integrated Products 

■ National Semiconductor 

WLCSP Forum Members 

■ Oki Semiconductor 

■ Pac Tech USA 

■ RF Micro-Devices 

■ Samsung Electro- 

Mechanics Col 

■ STMicroelectronics 

■ Texas Instruments 

■ UCP Processing Ltd. 

■ Vishay Siliconix 

52 


High-Speed Stencil Cleaning Techniques for IC 

Substrate-Level Assembly Lower Total Costs 

Printing-type processes have quickly 

become accepted in semiconductor 

and other sophisticated packaging 

applications. Stencil printing is an 

enabling technology for many waferbumping 

and similar uses. Integrating 

proven, innovative stencil cleaning 

process improvements into their 

operations is a very efficient way for 

contract manufacturing companies to 

control costs and improve yields. 

By Trevor Warren, DEK [dek.com] 

Processes performed at the chipsubstrate 

level include underfilling, 

encapsulation, and solder paste 

printing for bumping, as well as the 

surface-mount attachment of embedded 

decoupling capacitors. 

This understencil cleaning technology uses substantially less paper than conventional understencil 

cleaners. (DEK) 

Post-Singulation 

Because some of these processes are 

performed post-singulation, there is a 

great demand for solutions to maximize 

the throughput that can be achieved by 

using an automatic screen printer platform. 

Just as in the PWB surface-mount 

domain, every IC packaging process 

that impacts the total cycle time is under 

scrutiny, including periodic stencil 

cleaning operations. 

In the critical area of pre-placement, 

manufacturers face increasing pressure 

to maximize their throughput advantage. 

In under-stencil cleaning (USC), 

this equates to shorter and more efficient 

cleaning cycles, longer intervals 

between paper roll changeover and 

reduced changeover times. 

Analysis of Cleaning Costs 

To examine how the overhead time 

associated with USC may be reduced, it 

is important to analyze both the execution 

of the cleaning routine, as well as 

the actions needed to replenish the 

cleaning materials. 

A typical USC mechanism comprises 

a motor-driven roller loaded with an 

absorbent paper roll. 

When cleaning is required, the mechanism 

is moved into position under the 

stencil, and the paper is placed in direct 

contact with the stencil. 

The USC mechanism is then driven 

across the underside of the stencil to 

remove solder paste (or other material) 

from the lower surface of the stencil and 

the stencil apertures. Clean apertures are 

essential for paste deposit uniformity. 

There are usually three phases to a 

USC cycle, including a preliminary 

“wet” sweep, where a cleaning solvent is 

applied to the paper; a vacuum-assisted 

sweep to remove the bulk of the material, 

and a final “dry” sweep without solvent 

to remove any remaining material. 

The vacuum is applied through the 

cleaning paper, drawing solvent fumes 

and excess solder paste from the underside 

of the screen onto the cleaner paper. 

Reducing Waste 

Some systems allow the user to adjust 

this sequence, for example, to perform a 

second vacuum-assisted sweep if found 

to be necessary; or to perform the entire 

cleaning sequence twice if either the 

paste material or stencil characteristics 

make cleaning particularly troublesome. 

Between each sweep, the paper is 

indexed forward by a preset distance, so 

that clean paper is always used during 

each sweep. 

The specifications for the cleaning 

routine, including the sequence of operations 

and the distance by which the 

paper is indexed, are typically stored in 

the product file and retrieved by the 


53

machine each time the cleaning routine 

is invoked. 

The screen-cleaning rate, which defines 

the number of print cycles to be executed 

before the next cleaning routine is performed, 

is also stored in the product file. 

The time overhead—per unit produced—associated 

with cleaning is 

therefore dependent on the number of 

print cycles executed between screen 

cleaning operations and the total cycle 

time for cleaning. The latter is influenced 

by the number of sweeps included 

in the routine and the excursion 

speed of the cleaning head. 

Excessive consumption of cleaning 

paper will also act to increase the total 

cleaning overhead, since replenishing a 

spent paper roll incurs machine stoppage 

time. 

Cleaning Interval 

The maximum number of print cycles 

that can be performed before stencil 

cleaning is necessary 

is determined 

by the minimum 

acceptable limits 

for material transfer. 

Using a postprint 

inspection 

routine or statistical 

process control 

(SPC) software can 

aid in determining 

a suitable rate 

(Figure 1). Setting this rate too high will 

incur unnecessary print overhead. It 

will also also increase replenishment 

rates for consumables, including the 

paper roll and cleaning solvent. 

Some post-print inspection routines 

are able to invoke a USC cycle automatically, 

if preset thresholds for material 

transfer efficiency are breached. Again, 

suitable thresholds can be determined 

with the aid of SPC tools. 

Figure 1. This chart shows the paste transfer efficiency for materials and stencils. 

Cleaning Technologies 

Technological enhancements are 

required, however, if further reductions 

in cleaning overhead are to be achieved. 

These enhancements may include 

increasing the effective area of the 

cleaning head, thereby allowing the 

entire stencil area to be swept within a 

shorter duration. This is viable during 

both wet and dry phases, and can be 

achieved by redesigning the head to 

54 


keep a larger proportion of the paper in 

contact with the stencil. 

Other measures that combine certain 

phases of the wet, dry and vacuum cleaning 

sequence may reduce the overall 

cleaning cycle time without impairing 

the effectiveness of the cleaning action. 

For example, using a stronger vacuum 

and improved sealing enable some 

systems to perform vacuum cleaning 

concurrently with the dry sweep. This 

eliminates a complete phase of the USC 

cycle, bringing the potential to reduce 

the total cycle time by at least one-third. 

Replenishment Time 

The time spent replenishing the cleaning 

system is also important on overall 

productivity. 

Paper replenishment may occur 

before the start of a print run, at setup 

or changeover, or during the course of a 

print run. 

In any case, this is non-productive 

time that increases the cost of ownership 

of the machine. The replenishment 

process may take between five and 10 

minutes, depending on factors that 

include the operator’s skill and/or experience. 

Inefficient use of cleaning paper by 

advancing the paper further than is 

strictly necessary during any given 

cleaning routine will lead to excessive 

roll replenishment. 

Some cleaners, for example, always 

index the paper forward by the same 

distance, regardless of whether a wet, 

dry or vacuum clean has occurred. 

A shorter distance, however, may be 

acceptable after a dry sweep. 

Improvements will require that nextgeneration 

cleaning systems provide 

more flexible control over paper 

advance. Effective solutions to this challenge 

should deliver appreciable savings 

in paper consumption and thereby 

reduce replenishment overheads. 

Finally, measures to simplify replacement 

of the paper when the machine 

does have to be 

stopped should 

reduce the duration 

of the stoppage and 

thereby significantly 

improve productivity. 

A Better Spool 

Mechanism 

To replenish the 

paper roll in a conventional 

USC, the 

empty paper roller 

and take-up roller 

must both be 

removed. 

After positioning the new paper roller, 

the paper must be drawn through the feed 

mechanism and secured to the take-up 

roller. The operator must also set-up 

the correct paper tension and prime the 

paper feed mechanism before the printer 

is returned to its operational state. 

To address this aspect of cleaning 

overhead requires a complete revision 

of the traditional, dual-spool paper 

mechanism. These changes include a 

reduction in thenumber and complexity 

of operations required, the faster disposal 

of spent paper, and elimination of 

the need for manual adjustment of the 

mechanism before the machine can be 

returned to duty. 

Some USC systems now utilize a cassette-type 

paper feed mechanism, which 

can be replaced as a complete unit. 

Replacement is very fast, and does not 

involve the operator in actions such as 

routing and tensioning the paper. Not 

only does this lead to reductions in 

“machine stopped” time to carry out 

routine USC replenishment, but the 

level of skill required to complete the 

changeover is reduced. 

The potential for human error when 

installing the paper and setting the tension 

is also eliminated. 

Typically, the cassette containing the 

paper-roll mechanism is physically 

more compact than a comparable paper 

Figure 2. This graph shows all percentage release curves for stencils with 

various rectangular apertures. 

roll mechanism, enabling easier handling 

on the factory floor as well as 

space-efficient storage close to the point 

of use for fast retrieval. 

All the above factors contribute to 

reducing the time overheads associated 

with cleaning stencils during semiconductor 

package assembly, and lower the 

assembled cost per unit. 

Conclusion 

The advanced semiconductor packaging 

sector is now under pressures similar to 

those that have relentlessly challenged 

surface-mount assemblers to deliver 

economies of scale at the leading edge 

of technology. 

As printing-based processes for semiconductor 

packaging become mature, 

the industry is demanding innovative 

solutions to ensure maximum speed 

and efficiency, including new approaches 

to under stencil cleaning. Improved 

stencil cleaning is one available process 

improvement with clear performance 

and cost advantages. i 

Mr. Warren is Americas product manager 

for DEK. Prior to joining DEK in1995, he 

served in the British Armed Forces. During 

his tenure at DEK, Mr. Warren has been 

involved in the production and development 

of the company’s 265, 600, Europa and 

Galaxy platforms. [twarren@dek.com] 


55

INSIDE PATENTS 

Underfill: Patent Offers a New 

Approach to an Old Problem 

By A. Jason Mirabito [jmirabito@mintz.com] and 

Carol Peters [cpeters@mintz.com], Contributing Legal Editors, 

Mintz Levin Cohn Ferris Glovsky and Popeo P.C., Boston [mintz.com] 

PATENT NUMBER: 6,677,179 

TITLE: Method of Applying No-Flow 

Underfill 

INVENTORS: Yin Wusheng, 

Ning-Cheng Lee 

ASSIGNEE: Indium Corp. of America, 

Clinton, N.Y. 

FILED: Nov. 16, 2001 

ISSUED: Jan. 13, 2004 

The underfill process is a topic 

we have written about in the 

past. However, we find methods 

and techniques continue to develop in 

this field in an effort to solve the old 

problem of applying void-free underfill 

during chip mounting. 

We selected U.S. Patent No. 6,677,179, 

to feature because the patent discloses a 

simple, yet highly effective technique of 

applying a “no-flow” underfill. 

It is well-known that mismatches 

between such components as chips, 

laminates, and solders, due to differences 

in the coefficient of thermal 

expansion (CTE), may result in device 

failure during manufacturing or when 

chips are mounted on a PWB. Underfill 

encapsulants have been developed to 

help to reduce these failures. 

Most techniques are capillary flow 

underfill techniques, where a liquid underfill 

is placed around the periphery of a 

chip previously soldered onto a board. 

Capillary Action 

These methods use capillary action to 

draw underfill 

material across the 

entire underside of 

a chip. This action 

by itself, however, 

may not work particularly 

well with 

the many solder 

interconnection 

points of today’s 

chips if the underfill process. 

fails to reach the 

chip’s center. 

Another problem with present techniques 

involves two-step processes. The 

first reflow step mounts a chip onto a 

board, while the second step places 

underfill and cures the underfill material. 

Such two-step processes involve 

more time and, therefore, are more 

expensive to employ. 

One solution is a “no-flow” underfill. 

“No-flow” is applied to a board before a 

component/chip is soldered to it. This 

technique involves applying adhesive, 

including a fluxing agent, to a board 

surface before a chip is applied or soldered 

to the board. 

According to Indium’s ‘179 patent, a 

problem with prior no-flow processes 

include, for example, difficulty in applying 

heavily filled underfill. In addition, 

no-flow underfills may also result in 

significant differences between high 

CTEs of unfilled underfill and CTEs of 

other components, resulting in poor 

reliability. 

(A) Dipping Epoxy Flux 

(C) Placing Chip 

(B) Dispensing Filled Underfill 

(D) Reflow and Cure Underfill 

This drawing, based on the filed '179 patent, illustrates Indium's no-flow 

The ‘179 patent provides a process 

solution that follows the acronym KISS 

(Keep It Simple Stupid). As shown in 

the graphic, during a first step (A), a flip 

chip is picked up by suitable machinery 

and dipped into a tacky thermosetting 

flux with a well-defined thickness. 

A filled underfill is dispensed onto a 

board laminate or other substrate during 

a second step (B). 

Further, during a third step (C), the 

chip (previously dipped in the flux), is 

placed on the laminate so that solder 

contacts (BGAs) along the underside of 

the chip contact pads or contacts 

defined along the laminate. 

During a fourth step (D) of the process, 

the chip is soldered to the laminate and 

the underfill is cured via a reflow process. 

Conclusion 

The ‘179 patent further discloses the 

claimed underfill process eliminates the 

negative aspects of other processes and is 

compatible with high speed production. i 


INDEX TO 2006 ARTICLES 

Note: You may access these articles without cost on our web 

site: www.chipscalereview.com. Directories are shown in red. 

Departments 

Title, Author(s), Issue/Page 

Assembly Lines, Ron Iscoff 

Every issue, page 7 

Electronic Trends, Steve Berry and Sandra Winkler 

J-F/13, A/9, M-J/10, J/9, O/9 

Engineers’ Bookshelf, Staff 

M/63, J/87, 91, A-S/78 

In Retrospect, Dr. Subash Khadpe, J-F/15 

Inside Patents, A. Jason Mirabito and Carol Peters 

J-F/52, M/60, A/55, M-J/63, J/95, A-S/74, O/54, 

N-D/60 

It’s Academic, Dr. Guna Selvaduray, J/79 

Publisher’s Letter, Gene Selven 

Every issue, page 5 

Test Patterns, Paul Sakamoto 

J-F/10, M/12, A/12, M-J/12, J/13, A-S/12, O/10 

Trendlines, Terrence Thompson, M/9, J/83 

What’s New!, Staff 

J-F/56, M/62, A/53, M-J/61, J/97, A-S/72, O/51, N-D/56 

January-February 2006 

p. 31. Dispensing, encapsulating and 

underfilling: Picking the ‘right’ 

equipment for the job, Terrence E. 

Thompson, Senior Editor 

p. 40. International directory of 

dispensing system vendors 

p. 43. How flip-chip package interactions 

affect the manufacture of high-performance 

ICs, Robert Lanzone, Amkor Technology Inc. 

p. 49. Combining two acoustic microscope modes provides a 

way to disclose flip-chip defects, Tom Adams, Sonoscan 

March 2006 

p. 31. Wire bonding trends: shifting into 

overdrive, R. Iscoff 

p. 37. A comprehensive study of 

fine-pitch bonding reveals the 

importance of process control, 

Dr. Matthew Osborne, Kulicke & 

Soffa Industries 


production wire bonders 

p. 46. Wafer probing trends: tooling-up for the future, 

Clint A. Waggoner, Micromanipulator Co. 

p. 54. International directory of wafer probing stations 

p. 56. Thermal control with carbon-composite materials, 

Carol Burch and Kris Vasoya, ThermalWorks 

April 2006 

p. 30. IC packaging foundries: the big 

get bigger, R. Iscoff 

p. 34. Outsourced semiconductor 

assembly and test ‘05: boom cycle 

continued, but profits sagged, 

Dr. Subash Khadpe, 

Contributing Editor 

p. 40. International directory of IC 

packaging foundries 

p. 44. Wafer bonding reaches new highs…and lows!, 

T. Thompson 

p. 47. International directory of wafer bonding equipment 

and services 

p. 49. Wafer-level printing processes and capabilities, 

Mark Whitmore, DEK Printing Machines 

May-June 2006 

p. 30. Test & burn-in socket update: 

Gauging the impact of the EU’s 

RoHS Pb-free mandate, R. Iscoff 

p. 36. International directory of test and 

burn-in sockets 

p. 40. Photolithography tools for IC 

packaging: a quick review of 

equipment basics, T. Thompson 

p. 49. International directory of photolithography tools for IC 

packaging 

p. 51. Dicing before grinding for wafer thinning, 

Thomas Lieberenz and Devin Martin, Disco Corp. 

July 2006 

p. 36. The RoHS era begins, R. Iscoff 

p. 44. Choosing a wafer-bumping vendor 

without tears: where knowledge 

really is power!, T. Thompson 

p. 52. International directory of waferbumping 

service providers 

p. 55. Three-dimensional CSPs: making 

the transition from custom to 

commodity parts, Dr. Nicholas Colella, Tessera 

58 


p. 65. Post-dicing inspection: merits and technology, 

Udi Efrat, Camtek Ltd. 

p. 73. A brief primer on reflow ovens and processes, 

Erik Sventeckis, Kester 

August-September 2006 

p. 34. Singulation: refining the kindest 

cut of all, R. Iscoff 

p. 39. International singulation 

equipment manufacturer directory 

p. 42. Exploring options for keeping the 

heat out, T. Thompson 

p. 55. Challenges of soldering in a 

Pb-free world, R. Iscoff 

p. 58. International directory of lead-free, tin-lead and 

alpha-particle-free solder vendors 

p. 61. Electophoretic deposition technology: from cars to 

photoresists on 3D wafer structures, Lucas van den 

Brekel, Meco Equipment Engineers 

p. 63. Ten steps to effective opto package prototypes, 

Dr. Paul Magill, Avo Photonics 

October 2006 

p. 30. Packaged IC and WLP inspection trends: machines 

prove what the eyes can’t see, T. Thompson 

p. 37. International directory of failure analysis/defect 

inspection system manufacturers 

p. 40. Blade selection: your work is cut 

out for you!, R. Iscoff 


wafer-dicing/singulation 

blade vendors 

p. 47. A primer of probe card types 

and applications, 

J. B. Hollstein, SV Probe 

November-December 2006 

p. 26. Recipe for socket success: the 

‘right’ technology choices make 

the difference, R. Iscoff 

p. 32. International directory of test and 

burn-in socket vendors 

p. 36. Out damned spot! Today’s requirements 

are upping the stakes for 

cleaning systems, T. Thompson 

p. 41. Plasma cleaning equipment provider directory 

p. 43. Wet process cleaning systems provider directory 

p. 45. Comparing, contrasting and interpreting data for test 

socket signal integrity performance, Glenn Goodman, 

Advanced Interconnections Corp. 

p. 51. Plasma technology applications in IC assembly, 

Gene Dunn, Panasonic Factory Solutions America 

SURPRISE! 

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Camtek’s New Falcon 600 AOI 

System Is Designed for MEMS 

Camtek’s Falcon 600 AOI system is used for handling 

fragile devices including MEMS. 

Migdal Ha’emek, Israel—Camtek Ltd. has 

introduced the Falcon 600 for MEMS and 

other special applications. The unit is Camtek’s 

latest addition to its line of automated optical 

inspection (AOI) systems for the semiconductor 

manufacturing and packaging industries. 

The new model is dedicated to applications 

that require special handling and inspection 

capabilities,such as optoelectronic devices,MEMS, 

wafer-level packaging, and glass substrates. 

The Falcon 600 is designed to meet the growing 

demand from customers for specialized 

inspection alongside mainstream semiconductor 

wafer inspection, according to Camtek. 

With the Falcon 600, wafers on tape 

frames or expansion rings, as well as paperthin 

wafers and thick WLP bonded wafers, 

can be handled and inspected automatically. 

The system supports both framed and 

unframed wafers on a single platform. Its 

versatile structure and software-intense 

architecture help develop customized solutions 

and assure long service life as needs 

evolve. [camtek.co.il] 

Dage Announces Large-Board 

Format X-ray Inspection Unit 

Fremont, Calif.—Dage Precision Industries 

has introduced its XiDAT XD7800 large-board 

format digital x-ray inspection system. 

The system offers an inspection area covering 

610 x 762mm and fits circuit boards up 

to 617 x 883mm in size. 

It provides optimum resolution for large 

printed circuit boards and device failure 

analysis and combines the XiDAT (x-ray 

integrated digital acquisition technology) 

with a large inspection area. 

The XD7800 provides oblique angle views 

of up to 70° at any position, and 360-degrees 

around any point of the entire inspection 

area. The image quality and enhanced feature 

recognition of the Dage x-ray tube combined 

with the advanced analytical capabilities 

of its ImageWizard software provides 

world-class inspection quality. 

The XD7800 uses the Dage VR160 x-ray tube 

for sub-micron feature recognition to 950nm. 

Dage offers an optional NT250 x-ray tube with 

sub-micron feature recognition to 250nm. 

[dageinc.com] 

The XiDAT XD7800 inspects large boards with 

digital x-ray precision. 

Henkel Develops New Material For Flip-Chip Image Sensors 

Irvine, Calif.—Henkel has extended the 

company’s non-conductive paste (NCP) 

underfill encapsulant product line to address 

the growing image sensor market with the 

introduction of Hysol FP5110. 

The new material is specially formulated for 

flip-chip image sensor modules and provides 

excellent adhesion to both 2- and 3-layer 

flexible printed circuits by bonding effectively 

to both polyimide and epoxy adhesives, 

according to the company. [henkel.com] 

What’s New? 

Contact the Editor at chipscale@gmail.com 

60 


Integrated Technology Debuts PB6800 Probe Card Analyzer 

Tempe, Ariz.—Integrated Technology Corp. 

(ITC) has introduced an upgraded PB6500 

probe card analyzer for testing 300mm probe 

card arrays by expanding the capabilities of 

its PB6500 probe card analyzer. 

The new PB6800 analyzers offer a 300mmdiameter 

tungsten carbide measurement chuck 

with dual cameras and extended stage travel 

that allow probe arrays as big as 300mm in 

Micro Control Intros Low-Cost 

Production Burn-In System 

diameter to be touched-down without overhanging 

the chuck surface. 

Probilt’s measurement system can be 

expanded up to 12,000 test channels with 

optional software. 

Combined with the high chuck lift capability 

of 180Kg, the company says this makes it the 

ideal analyzer for all probe card technologies, 

including those being used to test the largest 

memory arrays on the newest test platforms. 

Micro Control’s LC-1 Logic Burn-In with Test 

System targets engineering characterization. 

Minneapolis, Minn.—Micro Control Co. has 

announced its LC-1 Logic Burn-In with Test 

System. The LC-1 is a sophisticated burn-inwith-test 

system suited for applications in engineering 

characterization, life testing and production 

screening of low-power logic devices. 

The LC-1 offers scan testing during burn-in, 

making it useful in meeting JTAG requirements. 

A unique feature of the LC-1 is its compatibility 

and adaptability to other vendors’ boards 

(610 x 318mm), which have been manufactured 

at sizes differing from the standard 

Micro Control burn-in board dimensions. 

This adaptability is accomplished through 

a proprietary adaptor that connects the 

burn-in board to the system electronics. The 

LC-1 It handles up to 64 burn-in boards sized 

at up to 610mm x 318mm with 128 I/Os. 

Alternatively, it can accommodate 32 

burn-in boards sized at up to 610 x 610mm 

with 256 I/Os. [microcontrol.com] 

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BACK OF THE BOOK 

5 Critical Challenges for 3D Packaging 

By Dr. David Tuckerman, Editorial Advisor [dtuckerman@tessera.com] 

There have been many impressive 

achievements in the drive 

to make electronics leverage 

the vertical dimension. 

Memory stacks have been in highvolume 

production for a decade, and the 

more complex configurations that have 

previously appeared only in packaging 

road-maps are also now in real products. 

Continuing Improvements 

The continuing improvements in thinning 

the various parts of a 3D integrated component 

will provide even more advantages. 

All of the upcoming predicted progress 

in 3D integration—and the products that 

rely on it—depend on the industry’s success 

in solving many technical challenges. 

I see at least five critical areas that need 

serious attention from the industry: 1) 

thermal management, 2) miniature 3D 

interconnect technologies, 3) planar 

passive components, 4) barrier coatings, 

and 5) infrastructure such as design 

tools and supply chains. 

Thermal management is widely seen 

as a huge challenge, perhaps the biggest 

in the whole electronics industry. 

High-level corporate marketing 

pitches from semiconductor companies 

now highlight low power and performance 

per Watt. Further integration and 

shrinkage only exacerbate the thermal 

density problem. 

Solutions that address thermal interfaces 

are needed, and some interesting 

options include phase-change materials 

and carbon nanotubes. Liquid cooling 

for heat removal is also promising, with 

evaporative technologies and microchannel 

approaches as leading candidates. 

Miniaturized 3D interconnectiontions 

will be important for ensuring 

that vertical electrical contacts do not 

become just a more advanced version of 

the bulky connectors used today. 

Conventional solder balls are working 

fine now for modest pincount devices, 

such as DRAMs, but more sophisticated 

integration will require much finer 

pitch contacts to ensure that miniaturization 

is still achieved. 

Passive Components 

Integration of passive components into 

planar configurations could be the most 

important step in leveraging vertical 

interconnect technologies. 

We have all seen printed circuit boards 

with low-profile components that are 

dwarfed—both vertically and horizontally—by 

large capacitors, inductors, and 

similar components. Integrated passives 

have been a target for a long time, but 

the time might be right for real breakthroughs 

now. The technology is getting 

better, and the motivation is increasing. 

One area that gets less attention is the 

need for impermeable but flexible coatings. 

As conventional packaging becomes 

severely shrunk or even eliminated, the 

mechanical and chemical protection that 

those structures created also disappear. 

Materials scientists need to develop 

novel solutions that restore these protective 

functions without adding bulk. 

Stacked packages, such as these sample 512Mb 

DRAMs, maximize board real estate by employing 

the vertical dimension. (Tessera) 

Infrastructure Elements 

Finally, as with any new technical 

approach, a set of infrastructure elements 

must be put in place. For 3D 

packaging, key pieces of this are design 

tools and supply-chain mechanisms. 

Industry-standard EDA tools would 

jump-start some progress, but there, we 

are still seeing proprietary point solutions 

vying for a leadership role. 

Most of the suppliers would be better 

off working towards common goals so 

that they can all find success in the 

growth of 3D technology. 

A solid and coordinated supply chain 

is also important. With chips coming 

from multiple suppliers, new and varied 

processes, novel materials, multiple levels 

of test and many other complications, 

there MUST be the appropriate 

communication and information 

exchange among supply-chain partners. 

I am looking forward to seeing how 

the industry solves these challenges, and 

I am confident that we will. i 

Dr. Tuckerman is Tessera’s chief technical 

officer and senior vice president. 

62 


ASSEMBLY LINES 

Continued from page7 >> 

Patrick, incidentally, 

retired after 31 

years in December. 

He plans to do voluntary 

work coaching 

and mentoring 

children, teaching 

and wants to 

Patrick Lam improve his tennis 

game. He’s been 

replaced by a team consisting of Lee 

Wai Kwong as CEO, James Chow as 

COO and Peter Lo as vice chairman. 

ASM Pacific is 54 percent owned by 

ASM International (ASMI), Bilthoven, 

The Netherlands. 

On November 27, at an Extraordinary 

General Meeting of Shareholders, management—with 

shareholder support—voted 

against an earlier proposal “by various 

shareholders” to split wafer processing 

and assembly/packaging activities. 

In a news release, management said 

the current structure, with front-end and 

backend activities “offers the greatest potential 

for ASMI’s future and for improving 

shareholder value.” [asmpt.com] i 

Contact the Editor at chipscale@gmail.com. 

Test Patterns Continued from page 11 >> 

A Much Different Experience 

Customers, meanwhile, are forced to 

make a lot of choices that are rearward 

looking. That is, the sunk cost of their 

last tester choice weighs very heavily on 

their next decision. This almost always 

means that they will be forced to choose 

the adequate model from their current 

vendor instead of the superior model 

from a new supplier. 

This is a much different experience 

than we have in our other technology 

choices today. 

For example, you can buy whatever 

PC meets your needs, but you have to 

compromise on testers. The culprit is 

the lack of standardization. Its close 

cousin is attending standards meetings, 

saying you are in favor of standardization, 

and then doing very little (e.g. “We wrote 

a STIL converter.”). 

The battle will take a long time, as it 

did with mainframes, but now is the time 

to join the fight for standards in the ATE 

industry. Down with the mainframe 

mentality! i 


INDUSTRY NEWS 

Worldwide Silicon Shipments Rise by 20 Percent 

San Jose—Worldwide silicon wafer area 

shipments increased by 20 percent last 

year over 2005, according to the SEMI 

Silicon Manufacturers Group (SMG). 

Silicon revenues also grew by 27 percent 

in 2006 compared to 2005, as a result of 

the larger contribution of 300mm wafers. 

Dr. Volker Braetsch, SMG chairman 

and Siltronic AG corporate vice president, 

noted in SEMI’s announcement 

that “2006 was a very robust growth 

year for the silicon wafer suppliers in 

both units and revenue. This was driven 

in a large part by the increased demand 

for memory products in both the 300mm 

and leading edge 200mm segments.” 

The SMG acts as an independent special 

interest group within SEMI. Data 

Annual Silicon Industry Trends 

presented in the table includes polished 

silicon wafers, epi, and non-polished 

wafers shipped by wafer manufacturers 

to end-users. [semi.org] 

Worldwide Silicon Data 2001 2002 2003 2004 2005 2006 

Area Shipments (MSI) 3,940 4,681 5,149 6,262 6,645 7,996 

Revenues ($B) 5.2 5.5 5.8 7.3 7.9 10.0 

(Source: SEMI) 

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ADVERTISER INDEX 

For more information about any of these advertisers and their products, visit www.chipscalereview.com 

or click on their link in the digital edition at www.chipscalereview.com-digital.com. 

Ace Tech Circuit atc-kr.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 

Alphasem (K&S) alphasem.com . . . . . . . . . . . . . . . . . . . . . . . . . 20 

Antares Advanced Test Technologies antares-att.com . . . . . . . . . . 48 

Aries Electronics arieselec.com . . . . . . . . . . . . . . . . . . . . . . . . . 39 

Carsem carsem.com . . . . . . . . . . . . . . . . . . . . . . Inside Back Cover 

Chip Scale Review chipscalereview.com . . . . . . . . . . . . . . 38, 46, 59 

CORWIL corwil.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19, 21 

Deweyl Tool Company Inc. deweyl.com . . . . . . . . . . . . . . . . . . . . 40 

DL Technology dltechnology.com . . . . . . . . . . . . . . . . . . . . . . . . 22 

E-tec Interconnect Ltd. e-tec.com . . . . . . . . . . . . . . . . . . . . . . . . 46 

F&K Delvotec fkdelvotec.com . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 

HCD hcdcorp.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 

HDI Solutions hdi-s.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 

Henkel electronics.henkel.com . . . . . . . . . . . . . . . . . . . . . . . . . . 12 

Indium Corp. of America indium.com . . . . . . . . . . . . . . . Back Cover 

Ironwood Electronics ironwoodelectronics.com . . . . . . . . . . . . . . . 60 

IWLPC smta.org/iwlpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 

Kester kester.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 

Kinesys Software kinesyssoftware.com . . . . . . . . . . . . . . . . . . . . 14 

Laurier Inc. laurierinc.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 

Lintec lintec-usa.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 

Machine Vision Products machinevisionproducts.com . . . . . . . . . . 16 

MEPTEC meptec.org . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 

Mintz Levin mintz.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 

Mirae mirae.com . . . . . . . . . . . . . . . . . . . . . . . . . . . 15, 17, 23, 25 

Mühlbauer muhlbauer.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 

NTK Technologies ntktech.com . . . . . . . . . . . . . . . . . . . . . . . . . . 4 

Orthodyne Electronics orthodyne.com . . . . . . . . . . . . . . . . . . 10, 11 

Pac Tech pactech-usa.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 

Panasonic Factory Automation panasonicfa.com . . . . . . . . . . . . . . . 9 

Plasma Etch plasmaetch.com . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 

Precision Contacts precisioncontacts.com . . . . . . . . . . . . . . . . . . 14 

Premier Semiconductor Services premiers2.com . . . . . . . . . . . . . 61 

Profab Technology profabtechnology.com . . . . . . . . . . . . . . . . . . . 42 

Robson Technologies Inc. testfixtures.com . . . . . . . . . . . . . . . . . . 3 

SEMITOOL semitool.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 

Sikama sikama.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 

SSEC ssecusa.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 31 

Surface Technology Systems stsystems.com . . . . . . . . . . . . . . . . . 6 

Tamarack Scientific Co. tamsci.com . . . . . . . . . . . . . . . . . . . . . . 54 

Transition Automation Inc. permalex.com . . . . . . . . . . . . . . . . . . 27 

Unisem unisem.com.my . . . . . . . . . . . . . . . . . . . Inside Front Cover 

Westbond westbond.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 

WinWay Technology winway.com.tw . . . . . . . . . . . . . . . . . . . . . . 47 

This index is provided as a service to advertisers and readers. Chip Scale Review does not 

assume any liability for errors or omissions in the listings. 

64

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